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Pull requests list

[aarch64] Mix the frame pointer with the stack cookie when protecting the stack backend:AArch64 backend:X86 llvm:codegen llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well
#161114 opened Sep 29, 2025 by PanTao2 Loading… updated Dec 2, 2025
1
50
[RegisterCoalescer] The COPY with the implicit-def of super register is not coalescable. backend:X86 llvm:codegen llvm:regalloc
#169997 opened Nov 29, 2025 by dianqk Loading… updated Dec 2, 2025
7
[MTE] Add an attribute to opt-in memory tagging of global variables while using fsanitize=memtag-globals (#166380) clang:codegen IR generation bugs: mangling, exceptions, etc. clang:frontend Language frontend issues, e.g. anything involving "Sema" clang Clang issues not falling into any other category llvm:codegen
#168535 opened Nov 18, 2025 by tarcisiofischer Loading… updated Dec 2, 2025
9
Skip stack protectors on alloca's which have new metadata to opt out backend:AArch64 llvm:codegen
#170229 opened Dec 2, 2025 by cooperp Loading… updated Dec 2, 2025
2
Fixes simple issue found static analyzer backend:AArch64 backend:PowerPC debuginfo llvm:codegen llvm:globalisel llvm:transforms
#169958 opened Nov 28, 2025 by Seraphimt Loading… updated Dec 2, 2025
10 tasks
6
[MachineBasicBlock] Don't split loop header successor if the terminator is unanalyzable backend:NVPTX llvm:codegen
#170146 opened Dec 1, 2025 by XChy Loading… updated Dec 1, 2025
1
3
[WoA] Remove extra barriers after ARM LSE instructions with MSVC backend:AArch64 llvm:codegen
#169596 opened Nov 26, 2025 by UsmanNadeem Loading… updated Dec 1, 2025
1
3
[Draft] Support save/restore point splitting in shrink-wrap backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 debuginfo llvm:codegen llvm:globalisel tools:llvm-reduce
#119359 opened Dec 10, 2024 by enoskova-sc Loading… updated Dec 1, 2025
21
[profcheck] Fix missing profile metadata in ExpandMemCmp llvm:codegen llvm:transforms
#169979 opened Nov 29, 2025 by jinhuang1102 Loading… updated Dec 1, 2025
3
[GOFF] Emit symbols for functions. backend:SystemZ llvm:codegen llvm:mc Machine (object) code
#144437 opened Jun 16, 2025 by redstar Loading… updated Dec 1, 2025
@redstar
41
[AMDGPU] Invert scc uses to delete s_cmp_eq* backend:AMDGPU llvm:codegen
#167382 opened Nov 10, 2025 by LU-JOHN Loading… updated Dec 1, 2025
48
[llvm][DebugInfo] Allow DIDerivedType as a bound in DISubrangeType debuginfo llvm:codegen llvm:ir
#165880 opened Oct 31, 2025 by tromey Loading… updated Dec 1, 2025
9
Minimal support of floating-point operand bundles backend:AMDGPU backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category floating-point Floating-point math llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well llvm:support llvm:transforms
#135658 opened Apr 14, 2025 by spavloff Loading… updated Dec 1, 2025
@spavloff
27
[clang][DebugInfo] Add virtual call-site target information in DWARF. backend:AArch64 backend:ARM backend:MIPS backend:RISC-V backend:X86 clang:codegen IR generation bugs: mangling, exceptions, etc. clang Clang issues not falling into any other category debuginfo lldb llvm:binary-utilities llvm:codegen llvm:ir
#167666 opened Nov 12, 2025 by CarlosAlbertoEnciso Loading… updated Dec 1, 2025
@CarlosAlbertoEnciso
45
[NFC][LLVM] Use @llvm.compiler.used/@llvm.used helpers in Clang and BitcodeWriter backend:AMDGPU backend:NVPTX llvm:codegen llvm:ir llvm:transforms PGO Profile Guided Optimizations
#162660 opened Oct 9, 2025 by jmmartinez Loading… updated Dec 1, 2025
@jmmartinez
23
[RegAlloc] Remove redundant parameters for weightCalcHelper (NFC). llvm:codegen llvm:regalloc
#170151 opened Dec 1, 2025 by hstk30-hw Loading… updated Dec 1, 2025
1
[RegisterCoalescer] Don't commute two-address instructions which only define a subregister backend:SystemZ backend:X86 llvm:codegen llvm:regalloc
#169031 opened Nov 21, 2025 by KRM7 Loading… updated Dec 1, 2025
6
[PHIElimination] Declare MachineLoopInfo dependency for Legacy PM backend:AMDGPU llvm:codegen llvm:regalloc
#169693 opened Nov 26, 2025 by PrasoonMishra Loading… updated Dec 1, 2025
7
[RFC][LLVM] Emit dwarf data for changed-signature and new functions debuginfo llvm:codegen llvm:transforms
#165310 opened Oct 27, 2025 by yonghong-song Loading… updated Nov 29, 2025
11
[InterleavedAccess] Construct interleaved access store with shuffles backend:AArch64 llvm:codegen llvm:transforms
#167737 opened Nov 12, 2025 by ram-NK Loading… updated Nov 28, 2025
10
[ISel] Introduce llvm.clmul intrinsic backend:RISC-V llvm:codegen llvm:ir llvm:SelectionDAG SelectionDAGISel as well
#168731 opened Nov 19, 2025 by artagnon Loading… updated Nov 28, 2025
78
[GlobalISel][LLT] Introduce FPInfo for LLT (Enable bfloat, ppc128float and others in GlobalISel) backend:AArch64 backend:AMDGPU llvm:codegen llvm:globalisel llvm:SelectionDAG SelectionDAGISel as well tablegen
#155107 opened Aug 23, 2025 by DenisGZM Loading… updated Nov 28, 2025
83
[AMDGPU] Allow negative offsets in scratch instructions backend:AMDGPU llvm:codegen llvm:globalisel
#166979 opened Nov 7, 2025 by gandhi56 Loading… updated Nov 27, 2025
1
@gandhi56
22
[regalloc][LiveRegMatrix][AMDGPU] Fix LiveInterval dangling pointers in LiveRegMatrix. backend:AMDGPU llvm:codegen llvm:regalloc
#168556 opened Nov 18, 2025 by vpykhtin Loading… updated Nov 27, 2025
7
[CodeGen] expand-fp: Change frem expansion criterion backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:SystemZ backend:VE backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen
#158285 opened Sep 12, 2025 by frederik-h Loading… updated Nov 27, 2025
39
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