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[PowerPC][MC] Diagnose out of range branch fixups backend:PowerPC
#165859 by nikic was merged Dec 2, 2025 Loading… updated Dec 2, 2025
[SelectionDAG] Remove Floating-point math llvm:SelectionDAG SelectionDAGISel as well
NoNaNsFPMath in visitFCmp backend:AArch64 backend:AMDGPU backend:MIPS backend:PowerPC backend:RISC-V backend:X86 floating-point #163519 by paperchalice was closed Nov 28, 2025 Loading… updated Dec 2, 2025
[LoopUnroll] Skip remainder loop guard if skip unrolled loop backend:AMDGPU backend:PowerPC backend:RISC-V debuginfo llvm:transforms
#156549 by jdenny-ornl was merged Oct 7, 2025 Loading… updated Nov 30, 2025
[clang] Refactor to remove clangDriver dependency from clangFrontend and flangFrontend backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:Hexagon backend:loongarch backend:MIPS backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:X86 bazel "Peripheral" support tier build system: utils/bazel clang:as-a-library libclang and C++ API clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:modules C++20 modules and Clang Header Modules clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category clang-tools-extra clangd flang:driver flang Flang issues not falling into any other category lldb llvm:mc Machine (object) code
#165277 by naveen-seth was merged Nov 23, 2025 Loading… updated Nov 29, 2025
Reland "RegisterCoalescer: Add implicit-def of super register when coalescing SUBREG_TO_REG" backend:AArch64 backend:loongarch backend:PowerPC backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#168353 by sdesmalen-arm was merged Nov 24, 2025 Loading… updated Nov 29, 2025
[LICM] Sink unused l-invariant loads in preheader. backend:AMDGPU backend:PowerPC clang:openmp OpenMP related changes to Clang clang Clang issues not falling into any other category llvm:transforms
#157559 by VigneshwarJ was merged Oct 30, 2025 Loading… updated Nov 28, 2025
CodeGen: Make all targets override pseudos with pointers backend:AArch64 backend:AMDGPU backend:ARM backend:CSKY backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:m68k backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:globalisel llvm:mc Machine (object) code llvm:SelectionDAG SelectionDAGISel as well tablegen
#159881 by arsenm was merged Nov 26, 2025 Loading… updated Nov 26, 2025
[VPlan] Use DL index type consistently for GEPs backend:PowerPC backend:RISC-V llvm:transforms vectorizers
#169396 by artagnon was merged Nov 26, 2025 Loading… updated Nov 26, 2025
[PowerPC] Fix unused variable after 0c9c62adf165eb backend:PowerPC
#169549 by boomanaiden154 was closed Nov 25, 2025 Loading… updated Nov 25, 2025
[PowerPC ]convert
(setcc (and X, 1), 0, eq) to XORI (and X, 1), 1 backend:PowerPC #168384 by diggerlin was merged Nov 25, 2025 Loading… updated Nov 25, 2025
CodeGen: Move libcall lowering configuration to subtarget backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168621 by arsenm was merged Nov 25, 2025 Loading… updated Nov 25, 2025
Reland "[RegAlloc] Fix the terminal rule check for interfere with DstReg (#168661)" backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#169219 by hstk30-hw was merged Nov 24, 2025 Loading… updated Nov 24, 2025
[RegAlloc] Fix the terminal rule check for interfere with DstReg backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc
#168661 by hstk30-hw was merged Nov 23, 2025 Loading… updated Nov 23, 2025
[PowerPC] TableGen-erate SDNode descriptions backend:PowerPC
#168108 by s-barannikov was merged Nov 17, 2025 Loading… updated Nov 21, 2025
CodeGen: Remove target hook for terminal rule backend:AArch64 backend:AMDGPU backend:ARM backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 llvm:codegen llvm:regalloc
#165962 by arsenm was merged Nov 12, 2025 Loading… updated Nov 21, 2025
[PowerPC] Replace vspltisw+vadduwm instructions with xxleqv+vsubuwm for adding the vector {1, 1, 1, 1} backend:PowerPC
#160882 by Himadhith was merged Nov 21, 2025 Loading… updated Nov 21, 2025
DAG: Use poison for some vector result widening backend:AArch64 backend:PowerPC backend:X86 llvm:SelectionDAG SelectionDAGISel as well
#168290 by arsenm was merged Nov 19, 2025 Loading… updated Nov 19, 2025
[SelectionDAGBuilder] Propagate fast-math flags to fpext backend:PowerPC llvm:SelectionDAG SelectionDAGISel as well
#167574 by mikolaj-pirog was merged Nov 15, 2025 Loading… updated Nov 19, 2025
CodeGen: Add subtarget to TargetLoweringBase constructor backend:AArch64 backend:AMDGPU backend:ARM backend:DirectX backend:Hexagon backend:Lanai backend:loongarch backend:MIPS backend:MSP430 backend:NVPTX backend:PowerPC backend:RISC-V backend:Sparc backend:SPIR-V backend:SystemZ backend:WebAssembly backend:X86 backend:Xtensa llvm:codegen llvm:SelectionDAG SelectionDAGISel as well
#168620 by arsenm was merged Nov 19, 2025 Loading… updated Nov 19, 2025
[PowerPC] Add initial support for AMO load builtins backend:PowerPC backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics clang Clang issues not falling into any other category llvm:ir
#167790 by maryammo was closed Nov 19, 2025 Loading… updated Nov 19, 2025
[PowerPC] Add custom lowering for SADD overflow for i32 and i64 backend:PowerPC
#159255 by AditiRM was merged Nov 19, 2025 Loading… updated Nov 19, 2025
[CGP]: Optimize mul.overflow. backend:AArch64 backend:ARM backend:loongarch backend:PowerPC backend:RISC-V backend:X86 llvm:codegen
#148343 by hassnaaHamdi was merged Nov 18, 2025 Loading… updated Nov 18, 2025
RegisterCoalescer: Enable terminal rule by default for AMDGPU backend:AArch64 backend:AMDGPU backend:Hexagon backend:NVPTX backend:PowerPC backend:RISC-V backend:SystemZ backend:WebAssembly backend:X86 llvm:codegen llvm:globalisel llvm:regalloc llvm:transforms
#161621 by arsenm was merged Nov 10, 2025 Loading… updated Nov 18, 2025
[MachineScheduler][AMDGPU] Allow scheduling of single-MI regions backend:AMDGPU backend:ARM backend:PowerPC backend:X86 mi-sched machine instruction scheduler
#128739 by lucas-rami was merged Feb 27, 2025 Loading… updated Nov 17, 2025
[CodeGenPrepare][X86] hasMultipleConditionRegisters - don't sink larger than legal integer comparisons backend:AArch64 backend:AMDGPU backend:PowerPC backend:X86 llvm:codegen
#166564 by RKSimon was closed Nov 10, 2025 Loading… updated Nov 16, 2025
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