EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!
Online viewer of Xschem schematic files
This project involves designing a single-core RISC-V CPU using Verilog. The design includes an Arithmetic Logic Unit (ALU) with flags, an assembly to machine code converter, a control unit, a microarchitecture and memory initialization to ensure proper functioning of the CPU.
A Verilog RTL design of a 1x3 packet router with a complete UVM testbench for verification. Includes FIFO buffers, FSM control, assertions, coverage, and synthesis support.
🚦 Build and verify a 1x3 packet router with modular Verilog RTL and a UVM-based environment for efficient functional testing and coverage.
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