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tests/pyb: Refactor pyboard tests to work on PYBv1, PYBLITEv1 and PYBD.
1 parent 7280bf4 commit 4b184d1

28 files changed

+185
-113
lines changed

tests/pyb/accel.py

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,9 @@
11
import pyb
22

3+
if not hasattr(pyb, 'Accel'):
4+
print('SKIP')
5+
raise SystemExit
6+
37
accel = pyb.Accel()
48
print(accel)
59
accel.x()

tests/pyb/adc.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
from pyb import ADC, Timer
22

33
adct = ADC(16) # Temperature 930 -> 20C
4-
print(adct)
4+
print(str(adct)[:19])
55
adcv = ADC(17) # Voltage 1500 -> 3.3V
66
print(adcv)
77

tests/pyb/adc.py.exp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
<ADC on 16 channel=16>
1+
<ADC on 16 channel=
22
<ADC on 17 channel=17>
33
50
44
25

tests/pyb/board_pybv1x.py

Lines changed: 39 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,39 @@
1+
# Test board-specific items on PYBv1.x
2+
3+
import os, pyb
4+
5+
if not 'PYBv1.' in os.uname().machine:
6+
print('SKIP')
7+
raise SystemExit
8+
9+
# test creating UART by id/name
10+
for bus in (1, 2, 3, 4, 5, 6, 7, "XA", "XB", "YA", "YB", "Z"):
11+
try:
12+
pyb.UART(bus, 9600)
13+
print("UART", bus)
14+
except ValueError:
15+
print("ValueError", bus)
16+
17+
# test creating SPI by id/name
18+
for bus in (1, 2, 3, "X", "Y", "Z"):
19+
try:
20+
pyb.SPI(bus)
21+
print("SPI", bus)
22+
except ValueError:
23+
print("ValueError", bus)
24+
25+
# test creating I2C by id/name
26+
for bus in (2, 3, "X", "Y", "Z"):
27+
try:
28+
pyb.I2C(bus)
29+
print("I2C", bus)
30+
except ValueError:
31+
print("ValueError", bus)
32+
33+
# test creating CAN by id/name
34+
for bus in (1, 2, 3, "YA", "YB", "YC"):
35+
try:
36+
pyb.CAN(bus, pyb.CAN.LOOPBACK)
37+
print("CAN", bus)
38+
except ValueError:
39+
print("ValueError", bus)

tests/pyb/board_pybv1x.py.exp

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
UART 1
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UART 2
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UART 3
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UART 4
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ValueError 5
6+
UART 6
7+
ValueError 7
8+
UART XA
9+
UART XB
10+
UART YA
11+
UART YB
12+
ValueError Z
13+
SPI 1
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SPI 2
15+
ValueError 3
16+
SPI X
17+
SPI Y
18+
ValueError Z
19+
I2C 2
20+
ValueError 3
21+
I2C X
22+
I2C Y
23+
ValueError Z
24+
CAN 1
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CAN 2
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ValueError 3
27+
CAN YA
28+
CAN YB
29+
ValueError YC

tests/pyb/can.py

Lines changed: 8 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -8,8 +8,8 @@
88
import micropython
99
import pyb
1010

11-
# test we can correctly create by id or name
12-
for bus in (-1, 0, 1, 2, 3, "YA", "YB", "YC"):
11+
# test we can correctly create by id (2 handled in can2.py test)
12+
for bus in (-1, 0, 1, 3):
1313
try:
1414
CAN(bus, CAN.LOOPBACK)
1515
print("CAN", bus)
@@ -273,18 +273,11 @@ def cb1a(bus, reason):
273273

274274
# Testing rtr messages
275275
bus1 = CAN(1, CAN.LOOPBACK)
276-
bus2 = CAN(2, CAN.LOOPBACK, extframe = True)
277276
while bus1.any(0):
278277
bus1.recv(0)
279-
while bus2.any(0):
280-
bus2.recv(0)
281278
bus1.setfilter(0, CAN.LIST16, 0, (1, 2, 3, 4))
282279
bus1.setfilter(1, CAN.LIST16, 0, (5, 6, 7, 8), rtr=(True, True, True, True))
283280
bus1.setfilter(2, CAN.MASK16, 0, (64, 64, 32, 32), rtr=(False, True))
284-
bus2.setfilter(0, CAN.LIST32, 0, (1, 2), rtr=(True, True))
285-
bus2.setfilter(1, CAN.LIST32, 0, (3, 4), rtr=(True, False))
286-
bus2.setfilter(2, CAN.MASK32, 0, (16, 16), rtr=(False,))
287-
bus2.setfilter(2, CAN.MASK32, 0, (32, 32), rtr=(True,))
288281

289282
bus1.send('',1,rtr=True)
290283
print(bus1.any(0))
@@ -299,11 +292,9 @@ def cb1a(bus, reason):
299292
bus1.send('',32,rtr=True)
300293
print(bus1.recv(0))
301294

302-
bus2.send('',1,rtr=True)
303-
print(bus2.recv(0))
304-
bus2.send('',2,rtr=True)
305-
print(bus2.recv(0))
306-
bus2.send('',3,rtr=True)
307-
print(bus2.recv(0))
308-
bus2.send('',4,rtr=True)
309-
print(bus2.any(0))
295+
# test HAL error, timeout
296+
can = pyb.CAN(1, pyb.CAN.NORMAL)
297+
try:
298+
can.send('1', 1, timeout=50)
299+
except OSError as e:
300+
print(repr(e))

tests/pyb/can.py.exp

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,7 @@
11
ValueError -1
22
ValueError 0
33
CAN 1
4-
CAN 2
54
ValueError 3
6-
CAN YA
7-
CAN YB
8-
ValueError YC
95
CAN(1)
106
True
117
CAN(1, CAN.LOOPBACK, extframe=False, auto_restart=False)
@@ -70,7 +66,4 @@ False
7066
(7, True, 6, b'')
7167
False
7268
(32, True, 9, b'')
73-
(1, True, 0, b'')
74-
(2, True, 1, b'')
75-
(3, True, 2, b'')
76-
False
69+
OSError(110,)

tests/pyb/can2.py

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,24 @@
1+
try:
2+
from pyb import CAN
3+
CAN(2)
4+
except (ImportError, ValueError):
5+
print('SKIP')
6+
raise SystemExit
7+
8+
# Testing rtr messages
9+
bus2 = CAN(2, CAN.LOOPBACK, extframe=True)
10+
while bus2.any(0):
11+
bus2.recv(0)
12+
bus2.setfilter(0, CAN.LIST32, 0, (1, 2), rtr=(True, True))
13+
bus2.setfilter(1, CAN.LIST32, 0, (3, 4), rtr=(True, False))
14+
bus2.setfilter(2, CAN.MASK32, 0, (16, 16), rtr=(False,))
15+
bus2.setfilter(2, CAN.MASK32, 0, (32, 32), rtr=(True,))
16+
17+
bus2.send('',1,rtr=True)
18+
print(bus2.recv(0))
19+
bus2.send('',2,rtr=True)
20+
print(bus2.recv(0))
21+
bus2.send('',3,rtr=True)
22+
print(bus2.recv(0))
23+
bus2.send('',4,rtr=True)
24+
print(bus2.any(0))

tests/pyb/can2.py.exp

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,4 @@
1+
(1, True, 0, b'')
2+
(2, True, 1, b'')
3+
(3, True, 2, b'')
4+
False

tests/pyb/extint.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
import pyb
22

33
# test basic functionality
4-
ext = pyb.ExtInt('Y1', pyb.ExtInt.IRQ_RISING, pyb.Pin.PULL_DOWN, lambda l:print('line:', l))
4+
ext = pyb.ExtInt('X5', pyb.ExtInt.IRQ_RISING, pyb.Pin.PULL_DOWN, lambda l:print('line:', l))
55
ext.disable()
66
ext.enable()
77
print(ext.line())

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