Timeline for Why does the ZX Spectrum ROM set I register, then wait 24 T-states?
Current License: CC BY-SA 4.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 26, 2024 at 12:07 | vote | accept | andrewf | ||
| Nov 18, 2024 at 13:33 | comment | added | andrewf | @HeartWare, That crossed my mind too, but the 257 0xFFs are at 0x3800, not 0x3F00, so it would need to put 0x38 into I not `0x3F. breakintoprogram.co.uk/hardware/computers/zx-spectrum/… (Not to mention the fact that the ROM uses IM 1, not IM 2.) | |
| Nov 18, 2024 at 11:11 | comment | added | HeartWare | @andrewf: In IM2, the interrupt routine jumps to the address contained at the word at address I*256+255 (or whatever is on the data bus at the time), and by setting it to $3F, it'll point to an area filled with $FF, leading it to jump to address $FFFF where you'd normally put a JR byte (can't remember opcode) which would then - combined with the opcode for the first byte in the ROM - a DI - would lead to a relative jump some bytes backward in memory, where you would then place an absolute JP to your interrupt routine. Perhaps the author thought of this when he decided to use $3F. | |
| Nov 18, 2024 at 10:41 | comment | added | andrewf | I wonder why the ROM’s authors didn’t just do: XOR A; LD I,A …unless to make that "less than $40" more explicit. | |
| Nov 18, 2024 at 9:41 | comment | added | the busybee | @andrewf The NOPs might be connected to setting the I register, so you might want to wait some time before splitting your question. | |
| Nov 18, 2024 at 9:07 | comment | added | andrewf | Brilliant, that answers the first part! Any idea about the "24 wait states"? (I’m inclined to mark as "accepted" and raise another question?) | |
| Nov 18, 2024 at 0:48 | history | answered | john_e | CC BY-SA 4.0 |