FYiFYI the int N CPU instruction doesn't cause an infinite handler loop, because this instruction pushes the address of the next instruction, so iret will continue from there.
Practical real-mode solutions
Don't enable any CPU features which may conflict with the BIOS interrupt vectors, e.g. don't enable machine check exceptions (in CR4.MCE), because they conflict with BIOS conventional memory size in int 12h.
Don't ever do a bound instruction in real mode, or install your own smart handler for int 05h, which checks that the return address is indeed a bound before.
Don't do any memory access wrapping the 16-bit offset (e.g. push at offset 1, pop at offset 0xffff, similarly for 32-bit push and pop, word-sized access at offset 0xffff, similarly for dword-sized access near 0xffff, similarly for qword-sized or tword-sized FPU access near 0xffff), don't do instructions longer than 10 bytes (including modifiers), don't do invalid push or pop instructions; these may trigger int 0x09 (RBIL), int 0x0c (RBIL) or int 0x0d (RBIL).
Interrupt vector list with conflicts
- int 00h: CPU 8086+ divide by zero
- int 01h: CPU 8086+ debugger single-step
- int 02h: NMI
- int 03h: CPU 8086+ breakpoint (int3)
- int 04h: CPU 8086+ overflow (into)
- int 05h: CONFLICT CPU 186+ bound range exceeded; BIOS print screen (typically this CPU interrupt causes an infinite interrupt handler loop, see above) (is it true that a smart handler can see the code being interrupted, detect the bound instruction easily? do most BIOSes have such a smart handler?)
- int 06h: CPU 186+ invalid opcode
- int 07h: CPU 286+ FPU device (coprocessor) not available
- int 08h: IRQ 0: timer; (CPU 286+ double fault; can't happen in real mode)
- int 09h: CONFLICT IRQ 1: keyboard; CPU 286,386 coprocessor segment overrun, this can happen by default in real mode (on CPU 486+, this generates an int 0dh instead) (is this conflict a real problem? maybe the keyboard IRQ handler is smart enough to detect that nothing came from the keyboard, and there won't be infinite loop upon the CPU interrupt; see also in RBIL)
- int 0ah: IRQ 2: cascade; (CPU 286+ invalid TSS; can't happen in real mode)
- int 0bh: IRQ 3: COM 2/4; (CPU 286+ segment not present; can't happen in real mode)
- int 0ch: HANG or CONFLICT IRQ 4: COM 1/3; (CPU 286+ stack-segment fault; can't happen in real mode; RBIL says that on 286 push with sp==1SP==1 in real mode the CPU shuts down, however on an IBM PS/2 286 in 86Box it just keeps going)
- int 0dh: CONFLICT IRQ 5: LPT 2; CPU 286+ general protection fault, it can happen in real mode (typically this CPU interrupt causes an infinite interrupt handler loop, see above) (CPU interrupt confirmed on an IBM PS/2 286 in 86Box, but QEMU 2.11.1 doesn't generate it) (how is this conflict resolved by the BIOS, i.e. how smart is a typical BIOS to detect the source of the interrupt, what does a typical BIOS do?)
- int 0eh: IRQ 6: floppy; (CPU 386+ page fault; can't happen in real mode)
- int 0fh: IRQ 7: LPT 1; (CPU reserved)
- int 10h; BIOS video services; (CPU x87 floating point exception is remapped to int 75h, see this answer and this answer)
- int 11h; BIOS equipment list; (CPU 486+ alignment check; can't happen in real mode)
- int 12h; BIOS conventional memory size; CPU 586+ machine check (not enabled by default, set CR4.MCE to 1 to enable it; can this happen in real mode?)
- int 13h; BIOS disk I/O; CPU SIMD floating point exception (not enbled by default, set CR4.OSXMMEXCPT to 1 to enable it) (can this happen in real mode?)
- int 14h; BIOS serial port I/O; (CPU virtualization exception; can't happen until virtualization is set up)
- int 15h; BIOS AT services, APM; (CPU control protection exception; can't happen after control protection is set up)
- int 16h; BIOS keyboard I/O
- int 17h; BIOS printer (parallel port) I/O
- int 18h; BIOS ROM-BASIC
- int 19h; BIOS reboot
- int 1ah; BIOS time services, MRCI services
- int 70h: IRQ 8: real-time clock
- int 71h: IRQ 9: redirected IRQ2
- int 72h: IRQ 10: reserved, none by default
- int 73h: IRQ 11: reserved, none by default
- int 74h: IRQ 12: reserved, none by default
- int 75h: IRQ 13: x87 floating point exception (remapped from CPU interrupt 10h)
- int 76h: IRQ 14: hard disk (HDD)
- int 77h: IRQ 15: reserved, none by default
