Timeline for Why does the 6502 read from the stack before writing it?
Current License: CC BY-SA 4.0
9 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 1 at 16:41 | comment | added | supercat | @lvd: Sending S to ADL early on in instruction execution for all instructions would avoid the need to have the contents of ADL at the start of the third cycle depend upon the instruction that was fetched. The cycle after the operand fetch cycle will always be either 01:SP, PCH:PCL, or 00dd where dd was the last value on the data bus, so if low-order address bus outputs have a multiplexer to select between ADL, PCL, and high-order address bus outputs augment those choices with 00 and 01, one can minimize the logic path between getting an opcode and deciding what to do on cycle 3. | |
| Oct 1 at 7:39 | comment | added | lvd | @supercat I feel it was just conventional in this specific case, as the initial S contents went to ALU to be incremented and since ALU has its own storage. | |
| Sep 30 at 18:47 | comment | added | supercat | ...a cycle off both JSR and RTS, and made their operation more intuitive (with JSR storing the address of its following instruction, rather than the address of its last byte). | |
| Sep 30 at 18:42 | comment | added | supercat | Does the 6502 always put the operand byte into S and reload S from ADL, or is that behavior unique to JSR? Because the 6502 was implemented with a single-metal NMOS process, the amount of space taken up by single-input single-output latches is relatively slight compared with the space taken up by signal routing. Where's the program counter stored? I wonder how much it would have cost to add transparent latches between the bus and the inputs to the program counter halves to allow JSR to latch both bytes of the new program counter address and then push the old one? That could have shaved... | |
| Sep 30 at 13:23 | comment | added | lvd | I looks more like the limitation of the following kind: 'no bus address valid signal'. Unlike 6800 which had such signal. | |
| Sep 30 at 13:04 | history | edited | cyco130 | CC BY-SA 4.0 | added 5 characters in body |
| Sep 30 at 13:01 | comment | added | cyco130 | True, no bus access is ever safe from side effects on 6502. But due to the design limitation of "exactly one memory access per cycle", it has to do spurious reads and writes for some instructions. | |
| Sep 30 at 12:58 | comment | added | lvd | "and a read is safer in the presence of memory mapped devices". Yet not completely safe, esp. when the read would acknowledge the interrupt, for example. | |
| Sep 30 at 12:51 | history | answered | cyco130 | CC BY-SA 4.0 |