The paper What Every Computer Scientist Should Know About Floating-Point Arithmetic uses the Cray's systems as an example of computers without a guard bit:

Although most modern computers have a guard digit, there are a few (such as Cray® systems) that do not.

Mathematics Written in Sand (William Kahan, 1983) suggests the same (for subtraction, specifically). But the hardware reference manual for the CRAY-1 and CRAY-2 describes how a guard bit is used for the add unit (that implements single-precision arithmetic only). So, I can think of two explanations:

1. The lack of guard bit affects other Cray systems.
2. The lack of guard bit affects the software implementation of double-precision arithmetic.

Is one (or both) of these right?

Edit: The Cray-1 Hardware Reference Manual does not explicitly state that a guard bit is used. Instead, it states that (page 3-24):

Floating point addition or subtraction is performed in a 49-bit register.

That is, addition is carried out with one extra bit. As Figure 3-4 shows the 49th bit as the leading 1 of the largest operand, it may suggest that the extra bit is used for an implicit, IEEE-754-like, leading bit. But floating-point numbers only had a 48-bit coefficient (page 3-11)

Floating point numbers are represented in a standard format throughout the CPU. This format is a packed representation of a binary coefficient and an exponent or power of two. The coefficient is a 48-bit signed fraction.

with no implicit bit (page 3-22)

A non-zero floating point number in packed format is normalized if the most significant bit of the coefficient is non-zero.

Unfortunately, I did not find an example in this manual. However, while it's a different model, there is one in the CRAY-2 Computer Systems Functional Description Manual. The octal representation of +1 is: 0 (signal) 40001 (exponent with bias 40000) 4000000000000000 (48-bit coefficient).

An Analysis of the Cray-1 Computer (Richard Sites, 1978) also states that a guard bit was used:

Addition is done with one guard bit and the result is truncated after normalization, with no rounding.

The paper What Every Computer Scientist Should Know About Floating-Point Arithmetic uses the Cray's systems as an example of computers without a guard bit:

Although most modern computers have a guard digit, there are a few (such as Cray® systems) that do not.

Mathematics Written in Sand (William Kahan, 1983) suggests the same (for subtraction, specifically). But the hardware reference manual for the CRAY-1 and CRAY-2 describes how a guard bit is used for the add unit (that implements single-precision arithmetic only). So, I can think of two explanations:

1. The lack of guard bit affects other Cray systems.
2. The lack of guard bit affects the software implementation of double-precision arithmetic.

Is one (or both) of these right?

Edit: The Cray-1 Hardware Reference Manual does not explicitly state that a guard bit is used. Instead, it states that (page 3-24):

Floating point addition or subtraction is performed in a 49-bit register.

That is, addition is carried out with one extra bit. As Figure 3-4 shows the 49th bit as the leading 1 of the largest operand, it may suggest that the extra bit is used for an implicit, IEEE-754-like, leading bit. But floating-point numbers only had a 48-bit coefficient (page 3-21)

Floating point numbers are represented in a standard format throughout the CPU. This format is a packed representation of a binary coefficient and an exponent or power of two. The coefficient is a 48-bit signed fraction.

with no implicit bit (page 3-22)

A non-zero floating point number in packed format is normalized if the most significant bit of the coefficient is non-zero.

Unfortunately, I did not find an example in this manual. However, while it's a different model, there is one in the CRAY-2 Computer Systems Functional Description Manual. The octal representation of +1 is: 0 (signal) 40001 (exponent with bias 40000) 4000000000000000 (48-bit coefficient).

An Analysis of the Cray-1 Computer (Richard Sites, 1978) also states that a guard bit was used:

Addition is done with one guard bit and the result is truncated after normalization, with no rounding.

The paper What Every Computer Scientist Should Know About Floating-Point Arithmetic uses the Cray's systems as an example of computers without a guard bit:

Although most modern computers have a guard digit, there are a few (such as Cray® systems) that do not.

Mathematics Written in Sand (William Kahan, 1983) suggests the same (for subtraction, specifically). But the hardware reference manual for the CRAY-1 and CRAY-2 describes how a guard bit is used for the add unit (that implements single-precision arithmetic only). So, I can think of two explanations:

1. The lack of guard bit affects other Cray systems.
2. The lack of guard bit affects the software implementation of double-precision arithmetic.

Is one (or both) of these right?

The paper What Every Computer Scientist Should Know About Floating-Point Arithmetic uses the Cray's systems as an example of computers without a guard bit:

Although most modern computers have a guard digit, there are a few (such as Cray® systems) that do not.

Mathematics Written in Sand (William Kahan, 1983) suggests the same (for subtraction, specifically). But the hardware reference manual for the CRAY-1 and CRAY-2 describes how a guard bit is used for the add unit (that implements single-precision arithmetic only). So, I can think of two explanations:

1. The lack of guard bit affects other Cray systems.
2. The lack of guard bit affects the software implementation of double-precision arithmetic.

Is one (or both) of these right?

Edit: The Cray-1 Hardware Reference Manual does not explicitly state that a guard bit is used. Instead, it states that (page 3-24):

Floating point addition or subtraction is performed in a 49-bit register.

That is, addition is carried out with one extra bit. As Figure 3-4 shows the 49th bit as the leading 1 of the largest operand, it may suggest that the extra bit is used for an implicit, IEEE-754-like, leading bit. But floating-point numbers only had a 48-bit coefficient (page 3-11)

Floating point numbers are represented in a standard format throughout the CPU. This format is a packed representation of a binary coefficient and an exponent or power of two. The coefficient is a 48-bit signed fraction.

with no implicit bit (page 3-22)

A non-zero floating point number in packed format is normalized if the most significant bit of the coefficient is non-zero.

Unfortunately, I did not find an example in this manual. However, while it's a different model, there is one in the CRAY-2 Computer Systems Functional Description Manual. The octal representation of +1 is: 0 (signal) 40001 (exponent with bias 40000) 4000000000000000 (48-bit coefficient).

An Analysis of the Cray-1 Computer (Richard Sites, 1978) also states that a guard bit was used:

Addition is done with one guard bit and the result is truncated after normalization, with no rounding.