Timeline for Why CPC464 display is less stable while reading from cassette?
Current License: CC BY-SA 3.0
6 events
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| Oct 28 at 21:24 | comment | added | Stéphane Gourichon | While interesting, I consider this answer to be wrong. To summarize the comments: the CPC display is not based on interrupts (the CPU can enable or disable interrupts at will, this won't affect the display) and the tape loading is not based on interrupts either (the first thing the firmware does when loading from tape is disable interrupts). More interesting comments attached to the question (instead of this answer). | |
| Oct 20 at 20:13 | comment | added | Tommy | A second bite of the cherry, seven years later: it's also untrue that "Most computers of this vintage used interrupts from the video controller chip to feed information to the display."; an appropriate correction would be "A couple of computers of an older vintage". Amongst those that do not "[use] interrupts ... to feed information to the display": the Apple II, TRS-80, PET, Atari 400/800, Vic-20, C64, Spectrum, CPC, BBC Micro, Electron, Oric, Dragon/Coco, MSX, TI-99/4[a]... | |
| Jul 12, 2018 at 14:45 | comment | added | Tommy | @StéphaneGourichon further to that, the tape input doesn't generate interrupts on a CPC. It's a CPU-visible bit that is polled, exactly like the ZX Spectrum, the MSX, etc. It isn't fed to an interrupt source as it is on e.g. the Commodores. | |
| Jun 15, 2016 at 9:48 | comment | added | mcleod_ideafix | The effect you describe in your answer is tipically found in the ZX81 / TS1500 computer, which effectively use NMI interrupts to build the display using some CPU power instead of a separate dedicated chip. It is not the case on the Amstrad CPC, which could keep showing a display even if the CPU is kept disabled (for example by pulling down BUSRQ) | |
| Jun 15, 2016 at 8:21 | comment | added | Stéphane Gourichon | Thank you @Chenmunka for your answer. Overall it makes sense, though AFAIK the details are different. The CPC has no interrupt to the CPU at the line level (there is a 300Hz interrupt available, 6 per frame), and the display works even if interrupts are disabled at the CPU level. It is possible because architecture interleaves access to the RAM by CPU and display at all times. Yet I hope we can get some details/confirmation in what the tape relay activation changes in this regard. | |
| Jun 15, 2016 at 8:00 | history | answered | Chenmunka♦ | CC BY-SA 3.0 |