AbsoluteƵERØ showed me that memory can be bypassed at the memory controller. https://security.stackexchange.com/questions/36592/can-linux-be-made-to-detect-foreign-connections-to-the-ram-bus

by showing me this patent: http://www.google.com/patents/US6745308

In the **Abstract** of the article, it says

> If particular memory controller components are idle, a memory client
> is informed that a bypassing of memory controller components is
> possible.

Does that mean that there *can't* be a bypass if the particular memory controller components aren't idle? (More quotes on "idleness" below)

If so, how can a memory controller be kept from an "idle" state?

-----------------------------------------

**Idleness Quotes**

>Only components that are idle or have no other memory requests to process may be bypassed.
> 
> The method as in claim 1, wherein the step of providing, to the client, the signal indicating the state of the memory controller
> includes providing a signal indicating a level of idleness associated
> with the memory controller pipeline.
> 
> The method as in claim 5, wherein determining a level of idleness
> associated with the memory controller pipeline includes analyzing
> memory request queues of a first component and a second component are
> empty.
> 
> A system comprising:providing the memory access request to a bypass
> module when the signal indicates the first component is idle;
> 
> Only components that are idle or have no other memory requests to
> process may be bypassed.
> 
> At least one embodiment of the present invention provides for a method
> of bypassing memory controller components. The method includes
> receiving a first memory request to read data from memory. In one
> embodiment, a bus interface unit receives the first memory request.
> The first memory request may be associated with a cache fetch request.
> The method includes determining if a first component and a second
> component of a memory controller are idle. The first component is a
> Northbridge client interface used to organize received memory
> requests. The second component is a Northbridge arbiter used to
> arbitrate, or select, requests from different clients, allowing
> received requests from all the clients to be processed. The result of
> determining if the first and second components are idle is provided as
> a signal to the host bus interface unit. The method also includes
> providing the first memory request to the first component, when the
> first component and the second component are busy. The method also
> includes determining, in the memory controller, if the first memory
> request is valid for access by bypassing the second component. In one
> embodiment the second component is used to generate commands to open
> closed pages of memory. If the memory request needs to access a closed
> page of memory, the memory request is considered invalid. The method
> also includes enabling the first memory request to be accessed by the
> second component, when the first memory request is considered invalid
> for bypass operations. The method further includes enabling the first
> memory request to be accessed by bypassing the first and second
> components, when the first memory request is considered valid.

with many more.