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AI Design Reshapes Data Management


Key takeaways: Integrating AI into chip workflows is pushing companies to overhaul their data management strategies, shifting from passive storage to active, structured, and machine-readable systems. As training and inference workloads grow, data movement, congestion, and energy efficiency become the dominant challenges, often surpassing raw compute capability. Proprietary and comple... » read more

CPO Is Extending The Limits Of What’s Possible In AI Data Centers


Key Takeaways I/O architecture must be co-designed with compute from day one. Partitioning SoCs into heterogeneous chiplets (compute, EIC, PIC, lasers) directly affects power delivery, floor-planning, interconnect topology, and system scalability. Successful CPO designs require architects to think in multi-physics terms, balancing electrical signaling, thermal stability, optical beha... » read more

Auto Security Accelerates With Standardization And Certified Silicon


Key Takeaways The automotive sector is actively developing and delivering secure parts and features ranging from secure boot to encrypted data and in-network protections. The cost of a breach can involve everything from ransomware to liability and/or damage to a brand. New standards are being introduced to ensure security, and technology developers are integrating cybersecurity requi... » read more

New Automotive Architectures Are Shaking Up Processor And Memory Choices


Key Takeaways Assisted and autonomous driving require more data from more sensors, and much faster processing of some of that data. The shift to software-defined vehicles and centralized intelligence makes it easier to identify where the most advanced processors and memories are required, and where older and less expensive technologies can be deployed. Technologies that were largely ... » read more

Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges


Key Takeaways • Chiplets and 3D-IC architectures add new thermal-mechanical stresses that can affect the reliability of entire systems. • As chiplets are assembled into packages, defectivity targets become more stringent for each component in a system. • Traditional silos are breaking down, forcing design teams to address issues such as materials choices that previously were handled by... » read more

Securing Hardware For The Quantum Era


Key Takeaways: Quantum threats to security are already real. Adversaries are already harvesting data that will be decrypted later by quantum computers. Quantum computers capable of breaking RSA and ECC may arrive as early as next year. Asymmetric encryption algorithms like RSA and ECC will become inadequate against quantum threats, while symmetric encryption (such as AES) is less vul... » read more

Multi-Die Assemblies Require More Detailed Test Plan Earlier


Key Takeaways Design for test takes on new urgency in complex multi-die assemblies, where it can be used to minimize downstream errors and the cost of fixing them. DFT needs to be increasingly detailed due to more connections and the inability to access some components. DFT strategies need to be developed earlier and may require multiple testing approaches. Multi-die assembl... » read more

Balancing Training, Quantization, And Hardware Integration In NPUs


Experts At The Table: AI/ML is driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down to discuss this with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Qu... » read more

Addressing Critical Tradeoffs In NPU Design


Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones. Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven W... » read more

How And Why To Optimize NPUs


Experts At The Table: AI/ML are driving a steep ramp in neural processing unit (NPU) design activity for everything from data centers to edge devices such as PCs and smartphones.  Semiconductor Engineering sat down with Jason Lawley, director of product marketing, AI IP at Cadence; Sharad Chole, chief scientist and co-founder at Expedera; Steve Roddy, chief marketing officer at Quadric; Steven... » read more

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