Low Power-High Performance

Top Stories

AI Power on the Edge

Architecting solutions for edge AI is not about minimizing cloud solutions or making small extensions of existing MCUs/MPUs. It's a hardware/softwa...

Scale Up, Scale Out Get a New Partner

For reaching farther into another data center, developers are now talking about scale-across.

Chiplets And 3D-ICs Add New Electrical And Mechanical Cha...

Reliability is now a system-level concern that includes everything from materials and packaging to testing with backside power.

UCIe’s Major Technical Components Are Now In Place

Version 3.0 of the interconnect standard doubles bandwidth and supports new use cases and enhanced manageability.

Minimum Energy Per Query

How much of the energy consumed in an AI chip is spent doing something useful? This question affects everything from software to system architectur...

Balancing Training, Quantization, And Hardware Integratio...

Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.

Addressing Critical Tradeoffs In NPU Design

Flexibility, future-proofing, and performance considerations for neural processing units.

How And Why To Optimize NPUs

PPA constraints need to be paired with real workloads, but they also need to be flexible to account for future changes.

Liquid Cooling Gains Traction In Data Centers

There are numerous ways to remove heat from chips, and more are on the way.

Will 2026 Be Dominated By AI?

Artificial intelligence has become central to almost all advances happening within semiconductors and EDA, but will that continue throughout the year?

More Top Stories »



Round Tables

Balancing Training, Quantization, And Hardware Integratio...

Evolving challenges and strategies in AI/ML model deployment and hardware optimization have a big impact on NPU architectures.

Addressing Critical Tradeoffs In NPU Design

Flexibility, future-proofing, and performance considerations for neural processing units.

How And Why To Optimize NPUs

PPA constraints need to be paired with real workloads, but they also need to be flexible to account for future changes.

Chiplet Ecosystem Slowly Emerges

Before the transition can be made from custom chiplet environments to a standardized off-the-shelf open marketplace, an ecosystem must be created.

When Can I Buy A Chiplet?

A chiplet ecosystem is under development, but many barriers must be overcome before a thriving marketplace can exist.

More Roundtables »



Multimedia

Memory For AI At The Edge

Why new LPDDR releases make them the memories of choice for many applications.

New Performance Requirements For Audio

Audio interactions with machines drive increasing demand for better sound quality.

Changes In Chip Architectures At The Edge

How to build an efficient and flexible multi-die system for edge AI.

LPDDR6: Not Just For Mobile Anymore

Why and how the go-to-DRAM for low-power devices is pushing beyond its roots.

Critical Factors For Storing Data In DRAM

New concerns and challenges for memory in AI data centers.

More Multimedia »



See All Posts in Low Power-High Performance »

Latest Blogs

A Bit About Memory

HBM4E Raises The Bar For AI Memory Bandwidth

The speed at which accelerators can be fed with data has become just as criti...
March 12, 2026
Best Of Both: LP & HP

Human-Centered Agentic AI Comes To RTL Verification

The long-term objective is to let engineers spend more time on what really ma...
March 12, 2026
At The Core

Rethinking Voice AI At The Edge: A Practical Offline Pipe...

Achieve low-latency, human-like dialogue without sending data outside the loc...
March 12, 2026
Everything Low Power

Serial Wire Debug (SWD) Protocol: Efficient Debug Interfa...

A compact, two-pin interface provides efficient access to debug and trace fea...
March 12, 2026
IP And LP In SoCs

Customizing Foundation IP For Ultra-Low-Voltage Designs

A case study on adapting memory compilers and logic libraries for power-criti...
March 12, 2026
Embedded ML Design

The On-Device LLM Revolution

Why 3B to 30B models are moving to the edge — and what that means for silicon.
February 20, 2026
MIPI And Beyond

Exploring The Latest Innovations In MIPI D-PHY And MIPI C...

Enhanced performance and flexibility for the next generation of high-speed ...
January 15, 2026
Inside Edge AI Processing

Next Generation AI: Transitioning Inference From The Clou...

High utilization, low memory movement, and broad model compatibility can coex...
December 11, 2025

Knowledge Centers
Entities, people and technologies explored


  Trending Articles

Making Hybrid Bonding Better

Why this technology is so essential for multi-die assemblies, and how it can be improved.

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers

Moving the power delivery network to the backside of a chip reduces congestion, but it introduces new challenges for fabs.

New Automotive Architectures Are Shaking Up Processor And Memory Choices

Exponential increases in data and a mix of performance requirements are driving a top-to-bottom rethinking of what works best where.

Chip Industry Week In Review

Rapidus' new $1.7B infusion; Intel and UMC leadership moves; faster EUV; $100B GPU deal; Arm-Tensor robocar; smartphone market to decline; HBF; $1B in AI chip funding; imec's mCFET study; monolithically stackable 1T1C 3D DRAM; automotive edge; Yongin cluster opening moved up; robovacuum hack; chip industry earnings.

Advanced Packaging Limits Come Into Focus

Mechanical and process control limits are now shaping what can be manufactured at scale.