tag: chiplets

Advanced Packaging Limits Come Into Focus
By Gregory Haley - 19 Mar, 2026 - Comments: 0

Key Takeaways: Packaging is now a performance variable. Substrate, bonding, and process sequence determine what can be built at scale. Warpage underlies most advanced packaging failures and gets harder to control as package sizes grow. Every proposed solution, such as glass, panel processing, and backside power, solves one problem while creating another. Moore's Law has shif... » read more

Replay‑based Validation as a Scalable Methodology for Chiplet‑based Systems (Intel, Synopsys)
By Technical Paper Link - 18 Mar, 2026 - Comments: 0

A new technical paper, "ODIN-Based CPU-GPU Architecture with Replay-Driven Simulation and Emulation," was published by researchers at Intel, Nvidia and Synopsys. Abstract "Integration of CPU and GPU technologies is a key enabler for modern AI and graphics workloads, combining control-oriented processing with massive parallel compute capability. As systems evolve toward chiplet-based archite... » read more

Pathfinding Method That Models ECC Overhead for Chiplet Interconnects (UCLA)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "Link Quality Aware Pathfinding for Chiplet Interconnects," was published by researchers at UCLA. Abstract "As chiplet-based integration advances, designers must select among short-reach die-to-die interconnect technologies with widely varying shoreline and areal bandwidth density, energy per bit, reach, and raw bit error rate (BER). Meeting stringent delivered BER ... » read more

Improving Yield Through Shared Data
By Ed Sperling - 11 Mar, 2026 - Comments: 0

Increasing complexity due to advanced packaging, multi-die assemblies, and more devices under test is having an impact on yield, which in turn slows time to market and impacts overall chip costs. What's needed is a way to share data that previously was siloed by chipmakers, fabs, and OSATs. Jayant D'Souza, technical product director at Siemens EDA, talks about the underlying drivers for sharing... » read more

Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs
By Yervant Zorian - 10 Mar, 2026 - Comments: 0

By Yervant Zorian and Sandeep Kumar Goel Anyone who follows the semiconductor industry knows that the accelerating performance, scale and energy efficiency demands of the AI revolution are outpacing the advances achievable by simply pushing the chip performance of monolithic, single-die designs. Multi-die design using 2.5D and 3D technologies has emerged as a necessity to keep the pace of in... » read more

How AI Is Changing Computing And Why Testing Is Critical
By Jeorge Hurtarte - 10 Mar, 2026 - Comments: 0

Artificial intelligence (AI) is transforming industries, enhancing our daily lives, and improving efficiency and decision-making, but its need for compute processing power is growing at an astonishing rate, doubling every three months (Figure 1). To maintain this pace, the semiconductor industry is moving beyond traditional chip development – it has entered the era of heterogeneous chiplets i... » read more

RPU: A Chiplet-Based Architecture To Address The Challenges of the Modern Memory Wall (Harvard University)
By Technical Paper Link - 04 Mar, 2026 - Comments: 0

Researchers from Harvard University have released “RPU -- A Reasoning Processing Unit”. Abstract “Large language model (LLM) inference performance is increasingly bottlenecked by the memory wall. While GPUs continue to scale raw compute throughput, they struggle to deliver scalable performance for memory bandwidth bound workloads. This challenge is amplified by emerging reasonin... » read more

How IP Subsystems For Chiplets Will Unlock Your Next Wave Of Innovation
By Robert Kruger - 26 Feb, 2026 - Comments: 0

After many years of hope, promises, and commercial challenges, a robust environment that supports multi-die design is now taking shape. These events represent a sea of change for semiconductor design and manufacturing when compared to the traditional single-die monolithic design approach. Moore’s Law drove these original and substantial monolithic design accomplishments. But the massive requi... » read more

AI Energy Gap And Chiplets: Why Data Movement Matters
By Ashley Stevens - 26 Feb, 2026 - Comments: 0

At the recent Chiplet Summit 2026 preconference tutorial, the panel session, “Best Way to Make Chiplets Work,” brought together leaders from across the semiconductor ecosystem to tackle one of the most pressing challenges in advanced system design: how do we make heterogeneous, multi-die systems operate as a cohesive, energy-efficient whole for AI? While much discussion focused on st... » read more

Verifying Scale-Up And Scale-Out In Data Centers
By Ed Sperling - 26 Feb, 2026 - Comments: 0

Semiconductor Engineering sat down to discuss challenges and solutions for data center build-out and build-up with Gordon Allan, Siemens EDA director of verification IP; Rishi Chugh, vice president of product marketing for network switching at Marvell; Saravanan Kalinagasamy, senior director of ASIC design and validation at Astera Labs; and Jalaj Gupta, product engineering lead at Siemens EDA. ... » read more

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