tag: low power

Customizing Foundation IP For Ultra-Low-Voltage Designs
By Daryl Seitzer - 12 Mar, 2026 - Comments: 0

By Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer Building a new system-on-chip (SoC) starts with assembling the right foundational elements—pre‑verified IP for logic, memory, I/O, and other essential functions. Standard IP solutions typically address most common design needs, but some projects call for more specialized approaches, especially when innovation is critical or when t... » read more

Minimum Energy Per Query
By Brian Bailey - 12 Feb, 2026 - Comments: 1

Key Takeaways Extracting heat from a chip faster is a short-term fix to a bigger problem. The longer-term challenge is how to reduce the amount of energy used per query. Data movement, guardbanding, and software inefficiency are key targets for the future. Heat is a serious problem within AI chips, and it is limiting how much processing can be done. The solution is either to... » read more

Limited by Power
By Brian Bailey - 11 Dec, 2025 - Comments: 0

AI is seen as a massive computation problem, but that is not the case, at least with the way that the problem is structured today. It is a data movement problem. This not only limits performance but represents most of the energy consumption. In addition, the industry spends most of its time and effort making small improvements that optimize aspects of the existing architecture, when what is ... » read more

PCIe Low-Power Validation Challenges And Potential Solutions
By Kunal Chhabriya - 13 Nov, 2025 - Comments: 0

As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

Why Data-Over-Sound Is An Integral Part Of Any IoT Engineer’s Toolbox
By Arm - 15 Oct, 2025 - Comments: 0

Data-over-sound technology such as Chirp presents a compelling solution for many device-to-device connectivity applications, particularly for use cases that require frictionless, low cost connectivity with nearby devices. Download this white paper to: Understand the fundamental concepts and benefits of data-over-sound connectivity Explore the key application areas within the Internet... » read more

The Criticality of Performance per Watt Optimization for AI Chip Development
By Synopsys - 03 Sep, 2025 - Comments: 0

Chip developers are seeing an urgent rise in demand for compute processing capability driven by AI workloads. This increase in compute requirements drives a corresponding increase in the demand for power consumption. For example, a ChatGPT query requires nearly 10 times as much power, on average, as a Google search. Power has traditionally been treated as a secondary constraint, with perform... » read more

Re-Architecting AI For Power
By Brian Bailey - 14 Aug, 2025 - Comments: 0

The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

SpiNNaker2 Neuromorphic Platform: HW-Aware Fine-Tuning of Spiking Q-Networks (TU Dresden Et Al.)
By Technical Paper Link - 05 Aug, 2025 - Comments: 0

A new technical paper titled "Hardware-Aware Fine-Tuning of Spiking Q-Networks on the SpiNNaker2 Neuromorphic Platform" was published by researchers at TU Dresden, ScaDS.AI and Centre for Tactile Internet with Human-in-the-Loop (CeTI). Excerpt "Spiking Neural Networks (SNNs) promise orders-of-magnitude lower power consumption and low-latency inference on neuromorphic hardware for a wide ran... » read more

Implications of Scalable Neuromorphic Computing (Sandia National Laboratories)
By Technical Paper Link - 30 Jul, 2025 - Comments: 0

A new technical paper titled "Neuromorphic Computing: A Theoretical Framework for Time, Space, and Energy Scaling" was published by researchers at Sandia National Laboratories. Abstract "Neuromorphic computing (NMC) is increasingly viewed as a low-power alternative to conventional von Neumann architectures such as central processing units (CPUs) and graphics processing units (GPUs), however... » read more

Exploring The Latest Innovations In MIPI D-PHY And MIPI C-PHY
By Mixel - 16 Jul, 2025 - Comments: 0

Introduction  In the ever-evolving landscape of high-performance camera and display technologies, MIPI D-PHY™ and MIPI C-PHY™ specifications continue to lead the charge, setting benchmarks for low power, low latency, and high bandwidth data transmission. Building on the insights from our previous article, “Demystifying MIPI C-PHY/D–PHY Subsystem” – ... » read more

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