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    Please read this thread on ARM community website. May be this is what you need! Commented Aug 21, 2017 at 7:22
  • @anandamu16: Can you elaborate on why you need this feature? You can of course always disable interrupt nesting simply by not using multiple priority levels. The M0+ lacks Cortex M3-style configurable sub-priorities however if you require priority arbitration up to but not including interrupt entry. It is difficult to help you without knowing the particular requirements. To be honest sub-priority masking is somewhat esoteric and should not normally be required unless shaving off the last very cycles of latency, in which case I suggest reconsidering using full preemption. Commented Aug 21, 2017 at 7:41
  • @Doynax: Actually I was recently working on Gpio Level Triggered Interrupts. But it was giving me multiple interrupts as soon as push button was pressed (This was because multiple interrupts occur within the time button press completed). I want to have interrupt only once till Gpio Handler exection gets completed. Also I don't want to disable GPIO Interrupt. Moreover, am I right that by default nesting is Enabled in ARM Cortex M0+ Interrupts? Commented Aug 21, 2017 at 9:36
  • Thanks Gaurav for the reference, I will check the link Commented Aug 21, 2017 at 9:38
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    @anandamu16: I am still not following you I'm afraid. A single interrupt handler never preempts itself on the Cortex M0+ without some significant contortions. Multiple different interrupt handlers, say on two GPIO ports, may preempt each other if the preempting interrupt source has been set to a higher priority. By default are all configured for the same priority level however and so this should not happen unless you've opted in. Commented Aug 21, 2017 at 11:02