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An5Drama
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In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

  • When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump operation be performed.

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

Edited:

In the doc of March 2023 version with Order Number 325462-079US, it doesn't list jmp in "Non-privileged serializing instructions" and "Privileged serializing instructions" although it seems that jmp is one serializing instruction. This where my confusion is because it suddenly use the "jump" term in one item of section 9.3 without reusing it in other items of that section.

Then after rereading the doc following the hints of the answers. In 10.9.2 Switching Back to Real-Address Mode, it says:

  1. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction queue and loads the appropriate base-address value in the CS register.

And it has one example asm code in 10.10.2 STARTUP.ASM Listing (Here I includes the line number) showing "flush" of "the instruction queue":

179 ; clear prefetch queue 180 JMP CLEAR_LABEL 

One more small question after reading the answers:

  1. Is jmp one serializing instruction?

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

  • When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump operation be performed.

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

Edited:

In the doc of March 2023 version with Order Number 325462-079US, it doesn't list jmp in "Non-privileged serializing instructions" and "Privileged serializing instructions" although it seems that jmp is one serializing instruction. This where my confusion is because it suddenly use the "jump" term in one item of section 9.3 without reusing it in other items of that section.

Then after rereading the doc following the hints of the answers. In 10.9.2 Switching Back to Real-Address Mode, it says:

  1. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction queue and loads the appropriate base-address value in the CS register.

And it has one example asm code in 10.10.2 STARTUP.ASM Listing (Here I includes the line number) showing "flush" of "the instruction queue":

179 ; clear prefetch queue 180 JMP CLEAR_LABEL 

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

  • When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump operation be performed.

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

Edited:

In the doc of March 2023 version with Order Number 325462-079US, it doesn't list jmp in "Non-privileged serializing instructions" and "Privileged serializing instructions" although it seems that jmp is one serializing instruction. This where my confusion is because it suddenly use the "jump" term in one item of section 9.3 without reusing it in other items of that section.

Then after rereading the doc following the hints of the answers. In 10.9.2 Switching Back to Real-Address Mode, it says:

  1. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction queue and loads the appropriate base-address value in the CS register.

And it has one example asm code in 10.10.2 STARTUP.ASM Listing (Here I includes the line number) showing "flush" of "the instruction queue":

179 ; clear prefetch queue 180 JMP CLEAR_LABEL 

One more small question after reading the answers:

  1. Is jmp one serializing instruction?
add the description of how the confusion is got.
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An5Drama
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In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing).

  • When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump operation be performed.

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

Edited:

In the doc of March 2023 version with Order Number 325462-079US, it doesn't list jmp in "Non-privileged serializing instructions" and "Privileged serializing instructions" although it seems that jmp is one serializing instruction. This where my confusion is because it suddenly use the "jump" term in one item of section 9.3 without reusing it in other items of that section.

Then after rereading the doc following the hints of the answers. In 10.9.2 Switching Back to Real-Address Mode, it says:

  1. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction queue and loads the appropriate base-address value in the CS register.

And it has one example asm code in 10.10.2 STARTUP.ASM Listing (Here I includes the line number) showing "flush" of "the instruction queue":

179 ; clear prefetch queue 180 JMP CLEAR_LABEL 

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing).

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

  • When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing). However, to maintain backwards and forward compatibility with code written to run on other IA-32 processors, it is recommended that the jump operation be performed.

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

Edited:

In the doc of March 2023 version with Order Number 325462-079US, it doesn't list jmp in "Non-privileged serializing instructions" and "Privileged serializing instructions" although it seems that jmp is one serializing instruction. This where my confusion is because it suddenly use the "jump" term in one item of section 9.3 without reusing it in other items of that section.

Then after rereading the doc following the hints of the answers. In 10.9.2 Switching Back to Real-Address Mode, it says:

  1. Execute a far JMP instruction to jump to a real-address mode program. This operation flushes the instruction queue and loads the appropriate base-address value in the CS register.

And it has one example asm code in 10.10.2 STARTUP.ASM Listing (Here I includes the line number) showing "flush" of "the instruction queue":

179 ; clear prefetch queue 180 JMP CLEAR_LABEL 
removed redundant word
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Sep Roland
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why Why do we need one jump after changing `PG` with `mov CR0, ... CR0`` when using non-completely serializing instruction?

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing).

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

why do we need one jump after changing `PG` with `mov ... CR0` when using non-completely serializing instruction?

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing).

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

Why do we need one jump after changing `PG` with `mov CR0, ...` when using non-completely serializing instruction?

In the Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3A 9.3 SERIALIZING INSTRUCTIONS

When an instruction is executed that enables or disables paging (that is, changes the PG flag in control register CR0), the instruction should be followed by a jump instruction. The target instruction of the jump instruction is fetched with the new setting of the PG flag (that is, paging is enabled or disabled), but the jump instruction itself is fetched with the previous setting. The Pentium 4, Intel Xeon, and P6 family processors do not require the jump operation following the move to register CR0 (because any use of the MOV instruction in a Pentium 4, Intel Xeon, or P6 family processor to write to CR0 is completely serializing).

"serializing instructions" will "serialize the instruction execution stream" before it runs to avoid the reordering.

Q:

  1. What is the purpose of the "jump instruction" after the special serializing instruction related with paging (i.e. mov with one CR0 register operand)? Does it imply refreshing the page table or others?

  2. What does "completely serializing" imply so that it doesn't need the jump following the "serializing instructions"?

[serialization] is about turning data structures into files or byte-streams or the reverse. Not about sequencing / ordering
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