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I have a custom header file example.h which has prototypes for a few functions. There is a .C file example.c that I implemented which "includes" (#include "example.h") and has the implementations of the functions that has prototype in example.h. Now, I have another function test.c that calls the functions that are prototyped in example.h and defined in example.c.

My make file is as follows 

test: test.o gcc -o test -g test.o test.o: test.c example.c example.h gcc -g -c -Wall test.c gcc -g -c -Wall example.c clean: rm -f *.o test

I get following message for the functions that are defined in example.c

Undefined first referenced symbol in file

function1 test.o

function2 test.o

function3 test.o

function4 test.o

ld: fatal: Symbol referencing errors. No output written to test

collect2: ld returned 1 exit status

* Error code 1

make: Fatal error: Command failed for target `test'

Any help is most appreciated.

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  • why aren't you linking example? you compiled it... Commented Feb 1, 2013 at 8:35

3 Answers 3

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%.o: %.c gcc -c -g -o $@ $^ test: test.o example.o gcc -o -g $@ $^

%.o: %.c This means any *.o file should be builded from its equivalen from c files.

example test.o should be builded from test.c and example.o should be builded from example.c

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The OP does not seem to be used to makefile rules and patterns, you should explain a little more. To clarify your answer you should : 1. Define what are $(CC), $(CFLAGS) and $(LDFLAGS) (give a little example with basic options), and 2. explain what are $@ and $^
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First of all, you must include the example.o file when generating the executable file : gcc -o test example.o test.o. Then, the dependencies you wrote for target test.o are incorrect. You should split it like this :

test: test.o example.o gcc -o test test.o example.o test.o: test.c gcc -c -Wall test.c example.o: example.c gcc -c -Wall example.c

Then, consider the use of variables to store the names of your object files, the flags you want to pass to the linker/compiler etc... This would make your life much easier.

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using the same rule for test.o: test.c and example.o: example.c is too much. you can reduce that in one rule. Use %.o: %.c instead and for the build command use gcc -c -Wall -g -o $@ $^
BTW the OP is using the -g as option in his gcc comands. you have to added it in your gcc command
I know that, but I wanted to give the OP a basic example without any use of special makefile rules (like .c.o: for instance). Clarify your answer for him and I'll upvote it :)
Thank you, Retiro. That worked. i'm getting warning such as : - implicit declaration of function XXXX and a few more. How do you fix it? PS: As much as I'd like to,being a newbie here, I cant upvote your answer. Thanks a lot for the help!
The "implicit declaration of function" means that at the time you call the function, it is not defined. Check whether you include all the header files you need or whether some declarations are missing (do not misunderstand : the declaration of a function is slightly different from the definition of a function). And for more convenient makefile use, you should look Mohamed's answer
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test.o: test.c example.c example.h
gcc -g -c -Wall test.c gcc -g -c -Wall example.c

as per your code test.o target is calling test.c example.c example.h target which i am not able to see.

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