I have a c++ project in which i need to define a variable in some CXX files. I have nearly 800 files out of which i need to define a variable for 200 files. So i was thinking to define it in makefile. So how can we do that.
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- Where are you having trouble? Also see Passing a gcc flag through makefile, Append compile flags to CFLAGS and CXXFLAGS while configuration/make, How to add compile flag -g to a make file?, Allowing users to override CFLAGS, CXXFLAGS and friends, Including a #define in all .c source files at compile time, Precedence of -D MACRO and #define MACRO etc.jww– jww2018-11-13 20:28:49 +00:00Commented Nov 13, 2018 at 20:28
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4 Answers
Just add -Dxxx=yy on the command line (xxx the name of the macro and yy the replacement, or just -Dxxx if there is no value).
It's not a Makefile command, it's part of the compiler command line options.
2 Comments
Akhil Pathania
What is xxx and yy
Fiddling Bits
It means,
xxx is the name and yy is the value. For example,#define xxx (yy) is -Dxxx=yy.Let's say you want a replacement for #define MYDEF
In your makefile you have the compiler command line, something like (simplest example):
g++ -o myfile.cpp To get that #define for every myfile.cpp just use -D like so:
g++ -DMYDEF -o myfile.cpp 
Comments
I would add the compiler flag to set a macro (-D for GCC) to the standard variable CXXFLAGS so it will be applied to any implicit rule compiler invocations:
CXXFLAGS += -DMY_DEFINE Then add that variable to any explicit rules you may have:
target: source.cpp $(CXX) -std=c++14 $(CXXFLAGS) ... Because the standard variables are only added with implicit rules.
Comments
Use can use a header file
defining.h:
#define deff 10 main.cxx or any file where you want to use
#include "definitions.h" The other way is while compiling give following arg g++ -DMYDEF file1.cpp file2.cpp ------ file200.cpp -o abc.exe
