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Generally, what processors follow is that level 1 cache is split while level 2 in unified cache. Why is it so? I'm not aware of any processor designed in the last 15 years that has a unified (L1) cache.

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  • One cache with the total number of read / write ports would be slower and higher power. And wouldn't have the physical proximity advantages of being near load/store ports vs. near front-end fetch stage. Commented Jun 9, 2020 at 17:38
  • Also related: Why is the size of L1 cache smaller than that of the L2 cache in most of the processors? re: why we have multi-level caches, with some more details about CPU caches. My answer there also describes why we make split L1 caches. Commented Jun 9, 2020 at 17:43
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