Strong Arm Latch Output When both inputs are at same voltage level

[Tinku_a]

Hi All

I am designing a Strong Arm Latch ( based on Razavi Paper) . When both the inputs are at the same voltage level , Expectation is that the latch should not be able to take a decision . But the simulation shows output going to HIGH . I am using 1.8V Supply & the common mode voltages are from 500mV to 1600mV. These are not MC sims and hence no mismatch between transistors and thus expecting that Latch cannot be able to make a decision.

 

[lichur_bagan]

Your simulation behavior is expected. In a Strong Arm Latch, when V+ = V-, the latch is metastable, but this point is unstable. Any infinitesimal perturbation—including simulator numerical noise—gets exponentially amplified by the cross-coupled inverters, causing one output to go high. Even with no transistor mismatch, the deterministic simulator will pick a side. Common-mode voltage (500 mV–1.6 V with 1.8 V supply) affects regeneration speed but not this fundamental behavior. In real silicon, thermal noise or mismatch randomly resolves the metastable state. Thus, seeing the latch “decide” in your simulation with equal inputs is normal and expected.