Non-Restoring Division For Unsigned Integer Last Updated : 23 Sep, 2025 Comments Improve Suggest changes 17 Likes Like Report The non-restoring division algorithm is a faster method to divide binary numbers. Unlike traditional division, it avoids repeatedly adding back the divisor, making it more efficient for computers to perform.It uses repeated subtraction and addition to find the quotient bits.If subtraction gives a negative result, the algorithm just adds in the next step instead of fixing it.Flow Chart of Non-Restoring Division For Unsigned Integer Steps Involved in the Non-Restoring Division Algorithm Step-1: First the registers are initialized with corresponding values (Q = Dividend, M = Divisor, A = 0, n = number of bits in dividend) Step-2: Check the sign bit of register A Step-3: If it is 1 shift left content of AQ and perform A = A+M, otherwise shift left AQ and perform A = A-M (means add 2's complement of M to A and store it to A) Step-4: Again the sign bit of register A Step-5: If sign bit is 1 Q[0] become 0 otherwise Q[0] become 1 (Q[0] means least significant bit of register Q) Step-6: Decrements value of N by 1 Step-7: If N is not equal to zero go to Step 2 otherwise go to next step Step-8: If sign bit of A is 1 then perform A = A+M Step-9: Register Q contains quotient and A contains remainder. ExampleLet’s divide the binary number 1011 (which is 11 in decimal) by 0011 (which is 3 in decimal) using the Non-Restoring Division Algorithm.Initialization: Dividend (Q) = 1011 Divisor (M) = 0011 Accumulator (A) = 0000 Number of bits (n) = 4 Step-by-Step Solution1. Initial Setup: Q = 1011 M = 0011 A = 0000 n = 4 2. First Iteration: Shift Left AQ: A = 0000, Q = 1011 becomes A = 0000, Q = 0110 Perform Operation: A = A - M = 0000 - 0011 = 1101 (2's complement of 0011) Sign Bit of A: 1 Update Q[0]: 0 Decrement N: N = 3 3. Second Iteration: Shift Left AQ: A = 1101, Q = 0110 becomes A = 1010, Q = 1100 Perform Operation: A = A + M = 1010 + 0011 = 1101 Sign Bit of A: 1 Update Q[0]: 0 Decrement N: N = 2 4. Third Iteration: Shift Left AQ: A = 1101, Q = 1100 becomes A = 1011, Q = 1000 Perform Operation: A = A - M = 1011 - 0011 = 1000 (2's complement of 0011) Sign Bit of A: 1 Update Q[0]: 0 Decrement N: N = 1 5. Fourth Iteration: Shift Left AQ: A = 1000, Q = 1000 becomes A = 0001, Q = 0000 Perform Operation: A = A + M = 0001 + 0011 = 0010 Sign Bit of A: 0 Update Q[0]: 1 Decrement N: N = 0 6. Final Adjustment: Sign Bit of A: 0 (no additional adjustment needed) Final Result: Quotient (Q) = 0011 (3 in decimal) Remainder (A) = 0010 (2 in decimal) Create Quiz Comment H him0000 Follow 17 Improve H him0000 Follow 17 Improve Article Tags : Computer Organization & Architecture Explore Basic Computer InstructionsWhat is a Computer? 6 min read Issues in Computer Design 1 min read Difference between assembly language and high level language 2 min read Addressing Modes in 8086 7 min read Difference between Memory based and Register based Addressing Modes 4 min read Von Neumann Architecture 5 min read Harvard Architecture 3 min read Interaction of a Program with Hardware 3 min read Simplified Instructional Computer (SIC) 4 min read Instruction Set used in simplified instructional Computer (SIC) 1 min read Instruction Set used in SIC/XE 2 min read RISC vs CISC 3 min read Vector processor classification 5 min read Essential Registers for Instruction Execution 3 min read Single Accumulator Based CPU Organization 3 min read Stack based CPU Organization 3 min read Machine Control Instructions in Microprocessor 4 min read Very Long Instruction Word (VLIW) Architecture 3 min read Input and Output SystemsPrimary Instruction Cycles 4 min read Machine Instructions 5 min read Instruction Formats 6 min read Difference between 2-address instruction and 1-address instructions 4 min read Difference between 3-address instruction and 0-address instruction 4 min read Register content and Flag status after Instructions 3 min read Debugging a machine level program 3 min read Vector Instruction Format in Vector Processors 7 min read Vector Instruction Types 4 min read Instruction Design and FormatALU Functions and Bus Organization 5 min read Computer Arithmetic | Set - 1 5 min read Computer Arithmetic | Set - 2 4 min read 1's Complement Representation vs 2's Complement Representation 4 min read Restoring Division Algorithm For Unsigned Integer 4 min read Non-Restoring Division For Unsigned Integer 3 min read Booth's Algorithm 4 min read How the Negative Numbers are Stored in Memory? 2 min read Microprogrammed ControlMicro-Operation 3 min read Instruction Set Architecture and Microarchitecture 3 min read Program Control Instructions 4 min read Difference between CALL and JUMP instructions 5 min read Hardwired and Micro-programmed Control Unit 3 min read Implementation of Micro Instructions Sequencer 4 min read Performance of Computer in Computer Organization 5 min read Introduction to Control Unit and its Design 5 min read Computer Organization | Amdahl's law and its proof 2 min read Subroutine: Nesting and Stack memory 3 min read Different Types of RAM (Random Access Memory ) 8 min read Random Access Memory (RAM) and Read Only Memory (ROM) 8 min read 2D and 2.5D Memory organization 4 min read Input and Output OrganizationPriority Interrupts 5 min read I/O Interface (Interrupt and DMA Mode) 4 min read DMA Controller 8257/8237 2 min read Computer Organization | Asynchronous input output synchronization 7 min read Programmable peripheral interface 8255 4 min read Synchronous Data Transfer in Computer Organization 4 min read Introduction of Input-Output Processor 5 min read MPU Communication in Computer Organization 4 min read Memory Mapped I/O and Isolated I/O 5 min read Memory OrganizationIntroduction to memory and memory units 2 min read Memory Hierarchy Design and its Characteristics 6 min read Register Allocations in Code Generation 6 min read Cache Memory 4 min read Cache Organization | Set 1 (Introduction) 3 min read Multilevel Cache Organisation 6 min read Difference between RAM and ROM 6 min read Difference Between CPU Cache and TLB 4 min read Introduction to Solid-State Drive (SSD) 4 min read Read and Write operations in Memory 3 min read PipeliningInstruction Level Parallelism 5 min read Execution and Throughput 5 min read Pipelining Types and Stalling 3 min read Computer Organization and Architecture | Pipelining | Set 2 (Dependencies and Data Hazard) 6 min read Last Minute Notes Computer Organization 15+ min read Like