Uploaded byDr. Shivananda Koteshwar
4Sem-HDL Programming Notes-Unit8-Synthesis
The document provides information about HDL synthesis basics. It defines synthesis as the process of converting HDL code into a optimized gate-level netlist. The synthesis process involves translation, optimization, and mapping stages. Translation converts RTL to boolean equations. Optimization improves the design based on constraints like timing, area, power. Mapping selects target library components to implement the boolean functions. The document also describes how an entity/module definition provides key synthesis information like block name, ports, sizes, values. Signal assignments are mapped to multiplexers during synthesis.
4Sem-HDL Programming Notes-Unit8-Synthesis
- 1. P e o p l e s E d u c a t i o n S o c i e t y S o u t h C a m p u s ( w w w . p e s . e d u ) Shivoo Koteshwar Professor, E&C Department, PESIT SC Synthesis Basics • Synthesis Basics: Highlights of Synthesis • Synthesis information from Entity and Module • Mapping Process and Always in the Hardware Domain. Reference Books: • HDL Programming (VHDL and Verilog)-‐ Nazeih M.Botros-‐ John Weily India Pvt. Ltd. 2008. UNIT 8: Synthesis Basics: Synthesis Basics: Highlights of Synthesis, Synthesis information from Entity and Module, Mapping Process and Always in the Hardware Domain 6 Hours EVEN SEMESTER 13 HDL DESIGN-‐4-‐CLASS NOTES – UNIT8
- 2. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 2 Synthesis: Synthesis is a process of converting HDL written in RTL format using either Verilog or VHDL to optimized mapped gate level netlist. • The RTL is optimized based on the constraints given – Timing, Area, Power etc • The netlist is mapped to the target library specified by user Synthesis is a 3-step process: Translation, Optimization and Mapping Translation: Conversion of RTL to Generic Boolean (GTECH equation). • Here while translating, it also does HDL Syntax/Rule checking Mapping: Mapping the netlist to target technology/library/standard cells. Here the tool maps Boolean functions to technology specific primitive functions. The mapping is done at 3 levels 1. Arithmetic function mapping 2. Sequential function mapping 3. Combinational function mapping Optimization: Boolean optimization is done based on the constraints specified (Area, Power, Timing etc). Some examples 1. Tree delay Minimization (Timing focused): Tree Height Minimization is an algorithm that is used during Timing Based high-level optimization. It restructures resources based on the timing constraints. In the example below, tool would choose the implementation on the right if D were the late arriving signal. If all 4 inputs had the same arrival time, DC would choose the implementation on the left.
- 3. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 3 2. Resource Sharing (Area focused) 3. Optimization to replace set of components by a complex gate NOTE: • Ultimate goal for HDL is to synthesize the system onto an electronic chip • Before synthesis, we need to simulate and test it. For testing, after we have written the logical code (RTL for the design), we need to write a testbench to give inputs and trigger the block so that we can monitor the output either in text format or in a waveform format
- 4. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 4 Synthesis Information from Entity and Module From entity/module, tool extracts four unique properties: 1. Name of the block (Functional unit) 2. The port list and whether they are input, output or inout 3. The bit size of the each of the pins 4. Possible values each of these pins can take Example:
- 5. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 5 Example2:
- 6. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 6 Mapping the signal assignment statement (y=x)
- 7. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 7 Mapping the signal assignment statement (y=2x+3)
- 8. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 8
- 9. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 9 Mapping the variable assignment statement • Verilog/VHDL does not distinguish between signal and variable assignment statements • Example: • The hardware domain is not capable of mapping the variable declaration and cannot distinguish between signal and variable • We notice that signal C takes the value of variable c1, so in hardware domain, c1 and C are one signal
- 10. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 10 Mapping the “if” statement (example1) Mapping the “if” statement (example2)
- 11. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 11 Mapping the “if” statement (example3)
- 12. HDL Design (4th Semester) UNIT 8 Notes v1.0 Shivoo Koteshwar’s Notes shivoo@pes.edu 12 Mapping the “if” statement (example4 –incomplete “if”)