Encoder decoder

Encoder decoder

• 1.
  Hanbat Hanbat National National University University Encoder-Decoder in VerilogEncoder-Decoderin Verilog Gookyi Dennis A. N.Gookyi Dennis A. N. SoC Design Lab.SoC Design Lab. July.15.2014
• 2.
  ContentsContents  Objectives  Encoder Decoder  Encoder-Decoder 2
• 3.
  ObjectivesObjectives  Wish todesign a system that encodes at one end and decode at the other end  Design a 4 to 2 encoder  Design a 2 to 4 decoder  Design a top level module that instantiates the encoder and the decoder 3
• 4.
  Block diagramBlock diagram The block diagram of the whole system is shown below: 4 4 to 2 Encoder 2 to 4 Decoder 4 Bit input 4 Bit output 2 Bit inout
• 5.
  EncoderEncoder  Truth tableof 4 to 2 encoder is shown below:  Output equations are as follows: out[0] = ((~in[3])&(~in[2])&(in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))out[0] = ((~in[3])&(~in[2])&(in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0]))) out[1] = ((~in[3])&(in[2])&(~in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0])))out[1] = ((~in[3])&(in[2])&(~in[1])&(~in[0])) | (((in[3])&(~in[2])&(~in[1])&(~in[0]))) 5 In[3] In[2] In[1] In[0] Out[1] Out[0] 0 0 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 1 0 0 0 1 1
• 6.
  EncoderEncoder  Verilog codefor encoder (submodule) 6
• 7.
  EncoderEncoder  RTL schematic 7
• 8.
  DecoderDecoder  Truth tablefor 2 to 4 decoder  Output equations are as follows: out[0] = (~in[0]) & (~in[1]) out[1] = (in[0]) & (~in[1]) out[2] = (~in[0]) & (in[1]) out[3] = (in[0]) & (in[1]) 8 In[1] In[0] Out[3] Out[2] Out[1] Out[0] 0 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0
• 9.
  DecoderDecoder  Verilog codefor decoder (submodule) 9
• 10.
  DecoderDecoder  RTL schematic 10
• 11.
  Encoder_DecoderEncoder_Decoder  Verilog code 11
• 12.
  Encoder_DecoderEncoder_Decoder  RTL schematic 12
• 13.
  Encoder_DecoderEncoder_Decoder  Full testbench 13
• 14.
  Encoder_DecoderEncoder_Decoder  Waveform 14