systemverilog and veriog presentation

Contents 1. Introduction 2. Work Carried Out In First Month • Fundamentals Of VLSI Design And Verilog Basics • VLSI:Syntax, Sematics, And Core Representation • Gate level modelling and Concept Wire 2.Work Carried Out In Second Month • Continuos Assignments and Data Operators • Verilog Operators Procedural Blocks and Assignments inVerilog 3.Work Carried Out Third Month • Introduction to SystemVerilog And Verification Enumerated Type • Access Methods Arrays and Queues

INTRODUCTION ● Verilog is a hardware description language used for developing code that describes digital systems and circuits. ● For the design and verification of digital and mixed-signal systems, Verilog is frequently utilized including both application-specific integrated circuits (ASICs) and field- programmable gate arrays (FPGAs). ● Developed by Gateway Design Automation and later acquired by Cadence Design Systems

Fundamentals Of VLSI Design And Verilog Basics Hardware Modeling There are two fundamental aspects of any piece of hardware: 1. Behavioral The behavioral aspects tells us about the behavior of hardware. What is its functionality and speed (without bothering about the constructional and operational details). 2. Structural The structural aspect tells us about the hardware construction. The design is comprised of which parts and how the design is constructed from these parts i.e. how they have been interconnected. .

VLSI Design Methodology ▪ Top-Down Design: Realizing the desired behavior by partitioning it into an interconnection of simpler sub behaviors. ▪Bottom-Up Design Realizing the desired behavior by interconnecting available parts components. ▪Mixed Top-Down and Bottom-Up Design It is a blend of top-down and bottom-up methodology.

Modeling Styles Verilog is both, behavioral and structural language. Designs in Verilog can be described at all the four levels of abstraction depending on needs of design. Behavioral Level: - Used to model behavior of design without concern for the hardware implementation details. Designing at this level is very similar to C programming. Dataflow Level [RTL]: - Module is specified by specifying the data flow. The designer is aware of how the data flows between registers. Gate Level: - Module is implemented in terms of logic gates & interconnections between them. Design at this level is similar to describing design in terms of gate level logical diagram. Switch Level: - lowest level of abstraction provided by Verilog. Module can be implemented in terms of switches, storage nodes & interconnection between them.

Behavioral Level Half Adder // Adder Module module half_adder(sum,carry,A,B); output sum; reg sum; output carry; reg carry; input A, B; always @(A or B) begin {carry, sum} = A + B; end endmodule

VLSI: Syntax, Sematics, And Core Representation Syntax & Semantics ▪All keywords must be in LOWER case i.e. the language is case sensitive ▪White spaces makes code more readable but are ignored by compiler ▪Blank space(b) , tabs(t) , newline(n) are ignored by the compiler ▪White spaces are not ignored by the compiler in strings ▪Comments // single line comment style /* multi line comment style */ Nesting of comments not allowed ▪Each identifier including module name, must follow these rules - It must begin with alphabet (a-z or A-Z) or underscore “_”. - It may contain digits, dollar sign ( $ ). - No space is allowed inside an identifier.

String ▪A string is a sequence of characters that are enclosed by double quotes. ▪Restriction on the string is that it must be contained on a single line only. ▪Strings are treated as a sequence of one – byte ASCII values. E.g. “Hello Verilog HDL” // is a string Identifiers ▪Identifiers are names given to objects so that can be referenced in the design. ▪Identifiers are made up of alphanumeric characters, the underscore( _ ) and dollar sign ( $ ). ▪Identifiers start with an alphanumeric character or an underscore. E.g. reg value // value is an identifier Escaped Identifiers ▪If a keyword or special character has to be used in an identifier, such an identifier must be preceded by the backslash ( ) character and terminate with whitespace (space, tab, or newline) E.g. reg //Keyword used valid! //Special character used

Number and System Representation ▪Two types of number specifications: - Sized <size>’<base format><number> e.g. 3’b101 - Unsized ’<base format><number> e.g. ’b101 ▪Size: Specified in decimal only and represents number of bits in number. Unsized numbers default to a compiler specific number of bits ( at least 32 bits ). ▪Base Format: Represent the radix. Legal base formats are decimal (‘d or ‘D), hexadecimal (‘h or ‘H), binary (‘b or ‘B) and octal (‘o or ‘O). Numbers, specified without a <base format> specification are decimal numbers by default.

▪Number: The number is specified as consecutive digits from 0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f. Only a subset of these digits is legal for a particular base. Uppercase letters are legal for number specification.

VLSI Data Types  Physical (NET) Data Types.  Abstract (Register) Data Types.  Constants.

Physical (NET) Data Types  Every declaration has a type associated with it.  All ports declaration are implicitly declared as wire (net) type. ▪ Net represents connection between hardware elements.  It does not store the value, therefore needs to be continuously driven i.e., Driver is implied when a net/wire is declared.  If the net has no driver (unconnected) its value is z. e.g., Tristate output.  If any input changes, assignment statement is evaluated & output is updated.

 “wor” performs “or” operation on multiple driver logic. E.g. ECL circuit  “wand” performs “and” operation on multiple driver logic. E.g. Open collector output  “trior” and “triand” perform the same function as “wor” and “wand”, but model outputs with resistive loads.

Abstract (Register) Data Types ▪ Registers represent data storage elements. ▪ Unlike a net, a register does not need a clock as hardware registers do. ▪ Default value for a reg type is ‘x’. reg reset; initial begin reset = 1’b1; #100 reset = 1’b0; end Constants/Parameter ▪ Constants can be defined in a module by the keyword parameter. ▪ Thus, can not be used as variables. ▪ Improves code readability.

Gate level modelling and Concept Wire ▪ Verilog language provides basic gates as built-in Primitives as shown. ▪ Since they are predefined, they do not need module definition. ▪ Primitives available in Verilog. i. Multiple input gates: and, nand, or, nor, xor, xnor ii. Multiple output gates: not,buf iii. Tristate gates: bufif0, bufif1, notif0, notif1 iv. Pull gates: pullup, pulldown

Multiple Input Gates ▪ Writing gate level hardware model for an and-gate ▪ module keyword implements a hardware ▪ unique name of the hardware (e.g. name of a human being) ▪ input, output ports or pins declarations ▪ by convention output ports are declared first ▪ body of module/hardware represents behavior ▪ concept of instantiation module and_gate_2_input(O, A, B); output O; input A, B; and and1(O, A, B); endmodule Multiple Output Gates ▪ These gates have only one input & one or more outputs. buf b1(WR1, WR2, WR3, WR); //instantiates buffer with three outputs ▪ Useful to increase Fanout of Signals.

Continuos Assignments and Data Operators Syntax of assign statement: Assign < drive_strength > < delay > < list_of_assignment > input A, B, C; output Y; Assign Y = ~(A & B) | C Continuous assignment characteristics: ▪ The left-hand side of an assignment must always be a scalar or vector net or a concatenation of scalar and vector nets. It cannot be a scalar or vector register. ▪ The assignment expression is evaluated as soon as one of the right-hand side operands changes and the value is assigned to left hand side. ▪ The operands on right hand side can be registers or nets or function calls. Registers or nets can be scalars or vectors. ▪ Delay values can be specified for assignments in terms of time units. Delay values are used to control the time when a net is assigned the evaluated value.

Verilog Operators Verilog Data Operators: - ▪ Arithmetic ▪ Bitwise ▪ Logical ▪ Reduction ▪ Shift ▪ Relational ▪ Equality ▪ Concatenation ▪ Replication ▪ Conditional Arithmetic Operators ▪ If any operand contains z or x the result is unknown ▪ If result and operand are of same size, then carry is lost ▪ Treats vectors as a whole value

Bitwise Operators ▪ Operates on each bit of operand ▪ Result is in the size of the largest operand Logical Operators ▪ Can evaluate to 1, 0, x values ▪ The results is either true (1) or false (0) Shift Operators ▪ Shifts the bit of a vector left or right ▪ Shifted bits are lost ▪ Arithmetic shift right fills the shifted bits with sign bit ▪ All others fill the shifted bits by zero Operators Operations Exampl

Relational Operators ▪ Evaluates to 1, 0, x ▪ Result in x if any operand bit is z or x Equality Operators ▪ assign Write Me = (wr == 1) && ((a >= 16’h7000) && (a < 16’h8000));

Looping Constraints There are four types of looping statements in Verilog:- ▪ While ▪ For ▪ Repeat ▪ Forever Loop Statements - while

Loop Statements - for Syntax: for (initial assignment; expression; step assignment) begin procedural assignment end

Loop Statements - repeat ▪ Keyword repeat is used for this loop. ▪ Executes the loop for fixed number of times. Loop Statements - forever Looping statements appear inside procedural blocks only. The forever loop executes continuously i.e. the loop never ends

Task, Functions and Compiler Directives

Introduction to SystemVerilog And Verification Data types

Verification with SystemVerilog

Data types, Enumeration and Constrants in VLSI Data type: • Relaxation of Verilog data type rules. logic -> reg/wire • 2-state data types to describe designs using abstract modeling. int i; // default value of i is 32’b0 • Enumerated types for design modeling (FSM states, opcodes, etc..) enum logic [1:0] {Red=0, BLUE=1, GREEN =2} color; • User-defined types that can be defined once and used throughout the design typedef enum logic [1:0] {RED =0, BLUE=1, GREEN=2} color, color n_color, o_color; • Supporting constructs for user-defined data types. typedef • Packages to share declarations amongst several modules. package... endpackage

Enumerated Type Access Methods

Arrays and Queues Fixed Size Array

Dynamic Array  A dynamic array is an unpacked array whose size is set or change at run time not compile time.  Can be allocated and resized during simulation.  Declared with empty subscripts [ ]. $size system function returns the size of fixed-array or dynamic array.  The space for a dynamic array doesn't exist until array is explicitly created at run time, space is allocated when new[number] operator is called. → number indicates the number of space/elements to be allocated. data_type array_name [ ]; // array declaration Array_name = new[ ]; // this operator allocates memory array name.delete(); // delete the array

Associative Array Methods  Used for sparse memories  Dynamically allocated, non-contiguous elements  Accessed with integer, or string index, single dimension  Great for sparse arrays with wide ranging index

Array Locator Methods  find(): returns all elements  find_index(): returns all indexes of array  find_first(): returns first element  find_first_index(): returns index of first element  find_last(): returns last element  find_last_index(): returns index of last element int d [ ] = `{2,3,4,56,67,45,4}; tqueue [ $ ]; initial begin tqueue = d.find with (item > 3); tqueue = d.find_last_index with (item == 4); end

Array Reduction Methods  These methods are used to reduce and unpacked array in single value.  sum(): return the sum of all elements of array  product(): return the sum of all elements of array  and(): return the sum of all elements of array  or(): return the sum of all elements of array  xor(): return the sum of all elements of array int d [ ] = `{2,3,4,56,67,45,4}; int summ, productt; initial begin summ = b.sum; productt = product; end

Queue Can provide easy sorting and searching Allocates extra space to quickly add extra elements Does not need new[ ] operator Push and pop operations are efficient Can add and remove elements from anywhere Declaration Initialization data_type queue_name [$]; q1 = {0, 3, 5, 8, 4}; int q1 [$]; q3 = {“ RED”, “BLUE”, “GREEN”};S bit q2 [$]; string q3 [$]; Byte q4 [$];

Data structures and multithreading 2.4.1: STRUCT: o A structure is a collection of variables and/or constants that can be accessed separately or as a whole o Allows logical group of signal to be combined together(example: control signal of a bus protocol) o The entire collection can be referenced using the name of the structure <structure_name>.<variable_name> instruction_word.address = 24’hF00000;

UNION: oUnion is a single element having multiple representations. oThe members that compose a union ,all share same storage area.

Tasks & Functions (Verilog vs System Verilog)

Threads : In system Verilog ,there are three types of threads. available other than begin …..end which are given below: 1.fork….join 2.fork….join_any 3.fork….join_none

INTERFACES AND CLOCKING STRUCTURES IN VLSI INTERFACE: o Interfaces are a major new construct in System Verilog, created specifically to encapsulate the communication between blocks. o Interface allows a smooth refinement from abstract system-level through successive steps down to lower RTL and structural levels of the design. o Interfaces also facilitate design re-use. Interfaces are hierarchical structures that can contain other interfaces.

CLOCKING BLOCK o Verilog primarily supported communication between different blocks through module ports o sv adds interfaces to encapsulate communication between different blocks thereby enabling users to easily change level of abstraction o an interface specifies signals or nets through which a test bench communicates with a DUT (device/design under test) o an interface does not specify any timing disciplines, synchronization requirements, or clocking paradigms o sv adds the clocking block that identifies clock signals, captures the timing and synchronization requirements of the blocks being modeled o clocking blocks are key elements in cycle-based simulation o they assemble signals synchronous to a particular clock and make their timing explicit o the test can be defined in terms of cycles and transactions rather than signals or transition time

Advanced Programming Constructs in VLSI Design Casting There are two types of casting in SV – static and dynamic casting Static Casting – at compile time Dynamic Casting – at run time Use cast system function – $cast(destination variable, source variable);

Interprocess Communication: Interprocess communication is a way to communicate between processes or testbench components. SystemVerilog provides three mechanisms for communication. Events: SystemVerilog event is used to synchronize between two or more processes or threads. An event is also a synchronization object that can be passed to a function or task or class constructor. This allows event sharing without declaring it as a global event.

Mailbox A SystemVerilog mailbox is a way of communication between different processes to exchange data. One process can put data into a mailbox that stores data internally and can be retrieved by another process. Mailbox behaves as first-in, first-out (FIFO). mailboxes are classified into two types based on their capacity constraints Generic mailbox Par  Bounded mailbox: If the size of the mailbox is defined then it is a bounded mailbox. When the mailbox is full, no further data can be put in the mailbox until an item or data is get from the mailbox.  Unbounded mailbox: The size is not defined. An unbounded mailbox has unlimited size.

Object oriented programming concept in vlsi design Why OOPs? o Helps in creating and maintaining large test-benches: One can create complex data types and tie them together with the routines that work with them. o Increase productivity: One can create test-benches and system-level models at a more abstract level by calling a routine to perform an action rather than toggling bits. One can work with transactions rather than signal transitions. o Allow the testbench to be reused: OOP decouples the test-bench from design details making it more robust and easier to maintain and reuse.

systemverilog and veriog presentation

systemverilog and veriog presentation

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systemverilog and veriog presentation