I have a question regarding the resolution of Numerically Controlled Oscillator where the most significant bit is being used as the digital clock. I am not including the phase look-up table where the phase accumulator is mapped to a sine wave and then fed to DAC. Instead, I want to generate a 13.56 MHz clock from a 200 MHz internal clock with a 32-bit accumulator. The frequency controlled word is 291,198,782. Since 200/13.56 = 14.749 is not an integer, the accumulator will roll over after 14 or 15 200 MHz clock cycles making the instantaneous period not equal to 13.56 but instead values like 200/14 = 14.28 MHz and 200/15 = 13.33 MHz. Does the output clock then average out to 13.56 MHz after a millions cycles? In other words, is average number of output 200 MHz cycles equal to 200/13.56 = 14.749?
1 Answer
Yes, the instantaneous frequency is dynamically changing, which itself can be described as a small angle frequency modulation of the desired 13.56 MHz carrier. The average frequency will be very close to 13.56 MHz as set by the overall precision or frequency step size.
The resolution is determined by the width of the NCO accumulator, and phase spurs in the output are determined by the phase truncation used (in the OP's case of just using the MSB, unless the output rate is an integer sub-multiple of the sampling rate, the phase truncation spurs will be significant!).
The relationship between the frequency resolution and accumulator size is summarized below:
$$F_\Delta = \frac{F_{clk}}{2^{accum}}$$
$$F_{out} = (FCW)F_\Delta = \frac{(FCW)F_{clk}}{2^{accum}}$$
Where:
$F_\Delta$: Frequency step size or resolution in Hz
$F_{clk}$: Clock (update) rate of NCO in Hz
$accum$: Width of accumulator in number of bits
$F_{out}$: Output frequency of NCO
$FCW$: Frequency Control Word in counts
A Python simulation to demonstrate the phase truncation spurs (including the expected odd order harmonics for a square wave and their aliases) is given below:
import numpy as np fclk = 200e6 # NCO Clock in Hz fout = 13.56e6 # Output freq in Hz acc_size = 32 # Accumulator size in bits nsamps = 2**25 # number of samples to simulate fcw = int(np.round(fout * 2**acc_size / fclk)) # determine FCW # generate output: n = np.arange(nsamps) acc = (n * fcw) % 2**acc_size output = acc >> (acc_size - 1) # MSB extraction With a 32 bit accumulator the frequency error is 15.42 mHz to get closest to the desired 13.56 MHz output with an integer FCW.
The resulting output is plotted below:
The FFT spectrum of the output is given below, scaled such that 0 dB is the power of the fundamental harmonic. If the simulation is repeated with a 45 bit accumulator, the error of the output frequency is reduced to $1.1 \mu$Hz, but the frequency spectrum will look identical to that shown below (as the spurious results are given by the phase truncation alone).
Please see DSP.SE#37803 for more technical details on the NCO and the phase truncation mentioned here.
- $\begingroup$ I think the only thing I'd add to this is that you could view the edge error of the clock either as FM, or phase jitter, or timing jitter. Which term to pick would depend on what you're doing with the information and, perhaps, what language anyone you're communicating with is most used to seeing. $\endgroup$TimWescott– TimWescott2025-02-08 18:13:42 +00:00Commented Feb 8 at 18:13
- $\begingroup$ @TimWescott yes good point! And the timing jitter perspective would likely be closer to the OP’s use case. $\endgroup$Dan Boschen– Dan Boschen2025-02-08 21:09:41 +00:00Commented Feb 8 at 21:09