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Questions tagged [symbol-timing]

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1 answer
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What algorithm is typically used for OFDM (4G/5G) timing recovery in FPGA implementation?
Tang Y's user avatar
  • 1
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1 answer
62 views

Sorry I am new to FPGA symbol timing recovery. Let's say I have a perfect channel (small AWGN noise is the only problem). The modulation format is BPSK, and the pulse shaping is square/rectangular ...
Linda's user avatar
  • 55
1 vote
1 answer
155 views

I knew there are several posts regarding a similar topic, however I would still ask the question to make sure I understand the symbol timing offset (STO) correctly. For instance, if a modem claimed to ...
DSP_Newbie's user avatar
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1 answer
61 views

I have to demodulate signal, modulate as a test signal in this way: ...
Nicola Altamura's user avatar
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1 answer
71 views

I have a question reg below statement: In Wi-Fi, symbol duration refers to the time it takes to transmit one symbol, which is a unit of data transmission, and it's a key factor in data rates and ...
user138602's user avatar
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1 answer
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I want to ask a question about symbol synchronization in demodulation process. As far as I understand, symbol synchronization block consists of three main components: time error detector, interpolator ...
unique's user avatar
  • 124
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1 answer
415 views

I'm looking for the solution for decoding FM0 (bi-phase space) encoded signal from RFID tag. Response from the tag starts with preamble and then followed by 16 bit random number. Link rate is 40kHz. ...
rf-engineer's user avatar
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0 answers
88 views

I have a simple BPSK system using RRC TX & RX filters with 10% excess bandwidth with a receiver that uses a symbol synchronizer of the common type consisting of a polyphase filter bank (performing ...
user67081's user avatar
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1 vote
0 answers
153 views

I have some questions about the M&M implementation of GNU Radio that uses complex samples. I started reading the implementation for real values: ...
Gabriel's user avatar
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0 votes
1 answer
254 views

E.g. the Symbol Sync block has a Loop Bandwidth, which (if I read the source right) ends up as a PI loop. I know what PID does mathematically, and what FIR and IIR ...
Thomas's user avatar
  • 115
1 vote
3 answers
281 views

I am trying to design a 2-GFSK receiver for acquiring IQ symbols. The aim is to implement the entire receiver chain but the decision stage. The 2-GFSK waveform is being generated by a standard IoT ...
Maaz Awan's user avatar
0 votes
1 answer
190 views

I am implementing a timing synchronization loop for a QPSK demodulator. I have chosen to use a Gardner timing error detector, which has often been mentioned. I am about to close my loop and I am ...
dsp_curious's user avatar
2 votes
0 answers
200 views

I am working on a simple MFSK modem for use on the HF band. I'm having trouble recovering the symbol timing information from the stream. With 2-FSK it's easy - just subtract one frequency from the ...
Stephen D.'s user avatar
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0 answers
170 views

I need to perform soft Viterbi decoding on a Manchester-encoded BPSK/QPSK signals. To that end, I need a floating point Manchester decoder. Most of the implementations I have seen operate on hard bits....
Moses Browne Mwakyanjala's user avatar
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1 answer
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I'm validating a C++ oQPSK receiver. The 5Mbps oQPSK signal is generated by a satellite emulator. The receiver structure goes as follows: SDR --> AGC --> Costa's Loop --> Delay --> ...
Moses Browne Mwakyanjala's user avatar

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