1
\$\begingroup\$

I am planning 6 layers PCB stackup for a product that will operate in very EMI noisy environments. The maximum speed on digital traces will be 50 MHz. I am planning the following stack-up

L1: High-speed (50 MHz) L2: GND L3: Low-speed signal L4: PWR L5: GND L6: Low speed signal

The ICs will be placed on L1 as well. Does above make sense? Also, when I go with a 4 Layer stackup as per below, would there be any disadvantages apart from less layers for low speed signals?

L1: High-speed (50 MHz) L2: GND L3: PWR L4: Low speed signal

And last question: Does it make sense to "burry" the high-speed traces between the GND layers, for instance according to below stack-up and if so from which frequency it would make sense?

L1: GND L2: High-speed signal (50 MHz) L3: GND L4: PWR L5: GND L6: Low speed signal
\$\endgroup\$
6
  • 3
    \$\begingroup\$ EMC is a complex, interconnected topic, and holistic in nature. There is generally very little that can be said about a problem without also completely describing the setup and environment: schematics, a loose description of all connections (cabling, type, what they might connect to, etc.), tentative PCB layout, assembly drawings, enclosure drawings, operating environment, applicable standards and test levels, etc., are required for a reasonably complete and confident answer. \$\endgroup\$ Commented Jun 29 at 23:08
  • 1
    \$\begingroup\$ Thank you. Understand, it's a broader topic and to needs a holistic view to be able to have an in-depth conversation. I was hoping to hear about some general guidance and best practise. \$\endgroup\$ Commented Jun 30 at 0:03
  • 2
    \$\begingroup\$ With digital signals you need to look at edge rate, not frequency. Your ‘low speed’ signals could easily be an issue. The pcb stack up is mainly so that your circuit does not radiate and for signal integrity. External interference is mainly controlled by filtering inputs/outputs. Sensitive circuits like RF are controlled by pcb layout and external shielding. \$\endgroup\$ Commented Jun 30 at 1:14
  • 1
    \$\begingroup\$ Well, see, that's the thing... For it to be any kind of general, or best practice, you have to look at the entire published and practiced corpus of EMC topics. We aren't going to [literally can't!] write entire books in answer to such a brief question. \$\endgroup\$ Commented Jun 30 at 2:09
  • 2
    \$\begingroup\$ Case in point: there are dozens of alternatives to (or in addition to) layer stackup alone. What about layout? Guard planes? Differential pairs? Signal levels? Metallic enclosure or shielding? Is it one board or a stack or a box or etc.? What is the frequency range of the interference? Of the signals (e.g. full expected spectra)? Is error correction available--how much does it really matter if interference occurs? Layer stackup is one of the lowest priorities; at best, it's an ill-defined question. \$\endgroup\$ Commented Jun 30 at 2:13

1 Answer 1

Reset to default
2
\$\begingroup\$

As already mentioned by others, the layer stackup is only one part out of dozens that are relevant for EMI.

Still it is possible to comment on your stackup proposals and give you some general guideance.

1) Signal to plane spacing

If your signals are routed directly above a continuous GND plane, they are less likely to radiate or pick up interference. The reason for this is that the loop area of the signal and GND return path is minimized. (EMI) current always flows and cross-couples in loops. So you want to have the high-speed layer and GND layer as close as possible (e.g. 50um distance in the vertical layer stackup).

2) GND to PWR spacing

If GND and PWR layers are close together they form a very good high frequency plate capacitor. Note that capacitance of a plate capacitor rises with inverted distance of the plates. So you want to have these layers as close as possible (e.g. 50um distance in the vertical layer stackup).

3) Low inductance vias

The vias should be low inductance, especially for connecting your components supply pins to GND and PWR layers (HF plate capacitor!). Via inductance rises with via length. So you want to have shortest possible connections from your component layer to GND and PWR layer (e.g. 50um distance from component layer to GND and PWR layers).

You might have noticed that it is hard to achieve 1) and 2) and 3) at the same time in a layer stackup, especially with a 4 layer board.

Welcome to trade-off and optimization land :-)

I would go with the following stackup for example for a total PCB thickness of 1mm (18um copper):

L1: High-speed signal & components (~50um) L2: GND (~50um) L3: PWR (~500um) L4: Low-speed signals (~50um) L5: GND (~50um) L6: Low-speed signals
\$\endgroup\$

Start asking to get answers

Find the answer to your question by asking.

Ask question

Explore related questions

See similar questions with these tags.