I am working on a board to distribute PPS in my house and came across this AppNote from Renesas. It shows that in a 50 ohm environment, I can just terminate to a 50 Ohm resistor, without worrying about the 7 ohm output impedance. I thought I would need to add a series resistor and a parallel resistor to match the impedance, but this says otherwise. Why is that the case? Is that specific to this clock-driving application?
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- 1\$\begingroup\$ This appnote talks about CMOS devices, which have input impedances in the GΩ range. And if you mean output impedance, some of the cases in the appnote do worry about it. Please specify the exact circuit you're talking about. \$\endgroup\$CL.– CL.2025-07-15 12:08:52 +00:00Commented Jul 15 at 12:08
- 2\$\begingroup\$ Are you sure you don't mean 7 ohm output impedance? Please draw where exactly you would put your series and parallel resistors. \$\endgroup\$Justme– Justme2025-07-15 12:11:07 +00:00Commented Jul 15 at 12:11
- \$\begingroup\$ Oops, I meant output impedance, I'll edit. \$\endgroup\$John Kha– John Kha2025-07-17 12:33:52 +00:00Commented Jul 17 at 12:33
- \$\begingroup\$ I was talking about the first circuit, thanks. The other cases are interesting, too. \$\endgroup\$John Kha– John Kha2025-07-17 12:35:11 +00:00Commented Jul 17 at 12:35
- \$\begingroup\$ Thanks, all. I will go with the series termination as recommended. I will try to post the schematic and board to GitHub and post here when I finish it. \$\endgroup\$John Kha– John Kha2025-07-17 12:42:13 +00:00Commented Jul 17 at 12:42
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1 Answer
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1 The app note describes a 7 Ω OUTPUT impedance, not input impedance.
There are several ways to use a 50 Ω line. You can terminate one end, either input or output, or you can terminate both ends. The purpose is to manage the reflections, to stop them from corrupting your logic levels. Each method has different strengths and weaknesses.
Terminating both ends, so 43 Ω series with the driver, and a 50 Ω shunt at the receiver, uses the most power, and only results in a half voltage swing at the far end. Both ends are available to absorb reflections, so this is tolerant of quite mis-matched line.
When terminating only the output, you can drive the input with the near zero impedance of a voltage buffer (app note figure 1), the high impedance of a current output (not shown in that app note, but look up LVDS drivers), or whatever you like. You get the full output voltage swing, but also the power consumption of the termination. The far end termination prevents reflections.
When terminating only the input, with a high impedance on the far end, you can use only one receiver position per line. The full voltage swing is only achieve at the far end, by reflection. Intermediate positions see a pathological signal, spending a significant time at half amplitude, the worst possible state for logic inputs. The input termination absorbs the far end reflection. This uses the least power, with no power consumption at all when the line is static.
If you are distributing a 1 PPS signal around the house, I would recommend using one buffer and one series terminated line per output for the simplest configuration and lowest power consumption. Any form of multi-drop cabling requires understanding termination, and allows interference between users, and is a false economy.
- \$\begingroup\$ Thanks! I meant output impedance. I am using their ICS524 1:4 clock driver to do the distribution, so no multi-drop for me. \$\endgroup\$John Kha– John Kha2025-07-17 12:33:10 +00:00Commented Jul 17 at 12:33