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I am designing a system where I have several daughter boards with voltage or current sensors (several or one on each board). One board is the master with the MCU.

Because the system is larger and in a high current and noisy environment, I have been using the logic to first condition/filter the analog signals from the sensors (some are differential, some are single ended) with a differential amplifier to turn the signal to analog differential with a common voltage of 1,25 V.

Then I use local ADC-s with a votage reference of 2,5 V (for best resolution) on each of the daughter boards. (The ADC-s support differential analog inputs) (I use differential analog signals here, because the traces on the PCB can be longer and run over high current signals on other layers).

For best signal integrity I first convert all of the signals on the digital side of the ADC (SCLK in, SCLK out, Dig OUT, CNVST in, CNVST out, CS in, Dig in -> most lines (7) for one ADC; CNVST out offers me a synchronization pulse on SCLK out for MSB, more info here: https://www.ti.com/product/ADS7223). ADS7223 connections with LVDS

More information on why I chose LVDS can be found here: https://www.ti.com/lit/ug/tidued8/tidued8.pdf

I will be also using 2 other types of ADC, because of the different number of signals on the daughter boards. The resoultion (number of bits) will be different between them.

The cables connecting the daughter boards to the master board will be around 1 meter in length and will be CAT5 cables so the differential pairs will be LVDS pairs for best noise immunity.

I have calculted that to transmit the signals in the necesary time windows (per sampling frequency) I need to run SCLK at 5 MHz or higher.

I will be using a STM 32 MCU on the main board. Because I will use SCLK out (SCLK return) for best oppertunity to read the data correctly (without delay/shift between SCLK and Dig OUT). I will be also using 1 SPI on the MCU as transmit only master to give the SCLK clock to all ADC-s, and other SPI-s as receive onyl slaves.

I also chose this aporach for best signal integrity before turning them to digital. Because I feared of voltage drop over the cable for analog signals if I would place all of the ADC-s on the main board.

The main down side of this approach is that I have to use many SPI slave receivers, because I think I can not connect the LVDS output together to one SPI (only if I use a multiplexer for both SCLK return and Dig out) mainly because of the speed and different bit numbers.

Questions:

1: Should I keep this approach or should I move all of the ADC-s to the main board, which would mean transmitting differential analog signals over differential pairs over a cable of > 1m ? (Should be OK, just checking for best option) (That would fix my problem in question 3)

2: If I should keep the current setting (ADC + LVDS on daugther boards), should I multiplex the LVDS outputs to a single SPI receiver on the MCU ? (I would like to avoid this, mainly because of delay and the different number of bits coming from each ADC) (Theoreticaly I have enough SPI lanes on the MCU to avoid this)

3: My problem with the current approach is the receiving of the signals. I receive the sinchronization pulse for the MSB (CONVST OUT), but I do not how to directly programme the desired behaviour where CONVST OUT (high -> low) signals the sinchronization pulse for MSB on a SPI receive only slave.

One possible solution for question 3 (and possiblity question 2):

I use the Enable pin on the pins on the LVDS receivers (DSLVDS1048 from Texas instrumetns for example), where I can switch the digital outputs to high impedance. Do you agree with this apporach? The only problem is how to implement this with the sinchronization pulse from CONVST OUT. I would appreciate any ideas. I would need to use a seperate LVDS receiver for getting CONVST OUT and then implementing an interupt in code to enable the main LVDS receiver. Would this cause too much of a delay? Enable features on the LVDS receiver

Thank you in advance

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  • \$\begingroup\$ 1 meter cable with 5MHz SPI sounds rather questionable in a noisy environment and might also get problems passing emissions testing. Why do you need to sample the ADCs that fast and why can't you miss a sample? \$\endgroup\$ Commented 2 days ago
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    \$\begingroup\$ @Lundin One of the plot lines in this question is to convert SPI signals to LVDS, and cross the 1 meter distance with LVDS. DSLVDS1047 and DSLVDS1048 in the schematic are the LVDS transmitter and receiver. \$\endgroup\$ Commented yesterday
  • \$\begingroup\$ @Lundin Outside my experience. For interest, page 7 of his referenced TI Designs: TIDA-060017 Transmitting SPI Signals Over LVDS Interface Reference Design notes "With LVDS interface and 10cm PCB trace, the maximum SPI clock speed is 22.3MHz. If the distance is increased to 3m for longer range communication, the maximum SPI clock speed is lowered to 9.7MHz under worst conditions." \$\endgroup\$ Commented yesterday
  • \$\begingroup\$ I would greatly appeciate knowing why someone has voted to close this question. It could be todiedup slightly BUT is a useful and highly technical question where there seems to be enough information to address the points raised. \$\endgroup\$ Commented yesterday
  • \$\begingroup\$ @RussellMcMahon An engineer shouldn't be thinking: can I get away with this bad idea? Instead they should follow best practices. Such as: keep SPI (or I2C etc) as board-to-board communication only. De-centralize design into individual modules with individual voltage regulators. Do not transmit analog signals over long wires. Etc etc. \$\endgroup\$ Commented yesterday

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1: Should I keep this approach or should I move all of the ADC-s to the main board, which would mean transmitting differential analog signals over differential pairs over a cable of > 1m ? (Should be OK, just checking for best option) (That would fix my problem in question 3)

The answer depends on the amount of interference in your environment, and on the acceptable amount of interference in the digitized waveform after the ADCs.

You’ll have the least interference if you place the ADCs next to the sensors, and cross the 1m distance with LVDS. But that complicates your design, because you’ll need LVDS transmitters and receivers.

On the other hand, a design where analog differential signals cross the 1m distance to the board with the ADCs and the MCU might be simpler. There’s a risk that the analog signals will pick up interference. Differential nature of the analog signal helps. Carefully considered shielding of the cables can help.

Would an experiment make sense where you’d measure worst case interference induced on a 1m differential analog connection?

Regarding questions 2 and 3. Instead of listening to the CONVST OUT bit, can the MCU trigger conversions through the CONVST pin? After conversions are complete, the MCU can retrieve the results without worrying about synchronization.

I am designing a system where I have several daughter boards with voltage or current sensors (several or one on each board). One board is the master with the MCU.

How many ADC (maximum) are going to be connected to one MCU? Are you using ADS7223 because it has two sample and holds and two ADC cores, so it can sample two signals synchronously? What’s the sample rate (for one current or voltage)? Some of the answers to your questions depend on these quantities.

A general description of the whole installation would help too. (Is it an electric car? Is it a robot arm?)

MISO lag due to propagation delay

Are you sure that lag in the MISO signal due to the round trip delay is actually a problem for a 5 MHz clock over a 1 meter distance? The propagation delays through the LVDS transmitter and receiver ICs are 1.7 ns and 2.7 ns . Propagation delay through a 1 meter of cable would be around 3 to 5 ns . That’s 10 to 20 ns round trip delay. Half-period of a 5 MHz clock is 100 ns.

Your hardware would be simpler if you don’t have to bring the lagged clock back around. You wouldn’t have to run another differential pair. One peripheral would do both MOSI and MISO, so you wouldn’t require the second SPI peripheral.

[This kind of lag would be a problem if the cable were longer. More application notes slyt441 and slla142. ]

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