Questions tagged [simulation]
About tools to simulate circuits. Specify the tool used.
2,171 questions
0 votes
1 answer
54 views
LTSpice: Zener diode breaks .op analysis?
I have a problem with .op analysis in LTSpice. Below you can see a part of an audio amplifier I'm tinkering with. For most of the time, I just simply used a voltage source instead of a zener diode. I ...
- 187
0 votes
1 answer
44 views
LTspice simulation results of current programmed mode control for buck converter not matching one shown in the book
I'm trying to simulate the Current Programmed Mode Control subcircuit for the buck converter described in section 18.5 of the Book Fundamentals of Power Electronics by Dragan Maksimović and Erickson, ...
- 379
0 votes
1 answer
104 views
Stepper Motor Control Circuit in Multisim (74193 + 74LS04 + 74LS08 + QBD139) —> LEDs Not Lighting
I’m working on a stepper motor control circuit in Multisim using the following ICs: 74193 (4-bit binary counter) 74LS04 (inverter) 74LS08 (AND gate) QBD139 (NPN-Transistor) The goal is to simulate a ...
9 votes
4 answers
2k views
In a seven segment display, why does my "6" looks like a small letter "b"
I have made this circuit on Proteus, a simple BCD to 7-segment display: But the segments for 6 and 9 are not completely lit. What could be the potential reasons? The decoder IC is CD4511 and a common ...
- 109
0 votes
0 answers
49 views
How do I simulate the RDS value in LTspice?
I'm having trouble finding any material, for example: a manual or video that shows how to measure the RDS of a MOSFET in LTSpice.I want to understand the behavior in this circuit I've built.
- 509
1 vote
1 answer
86 views
Will the TLV7031 low-voltage comparator work with this input voltage?
Since I have not worked with low power currents in the uA range before, I would like to ask you before starting the design. I have simulated the circuit below and have a few questions about it. When ...
- 51
3 votes
2 answers
133 views
JK flip flop behavior on startup in Verilog
I've tried to implement a JK flip flop in Verilog, but while testing, I found that whatever inputs of j and k I give on startup, until I reset the flip flop (j=0, k=1), the outputs will not be seen ...
- 31
0 votes
0 answers
56 views
Simulate induced voltage in PCB loop because of a second loop that is fed by a given voltage signal waveform
I fear that might be too broad but for educational experiments, I would like to know as specifically as possible how to simulate the induced voltage in a PCB loop (let´s call it Loop 1) as an effect/...
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