Pinned Loading

1. hgdb hgdb Public

   Hardware generator debugger

   C++ 77 2

2. fsim fsim Public

   Fiber-based SystemVerilog Simulator.

   C++ 25 1

3. kratos kratos Public

   ⚔️ Debuggable hardware generator

   C++ 71 10

4. pysv pysv Public

   Running Python code in SystemVerilog

   Python 72 15

5. cgra_pnr cgra_pnr Public

   Fast PnR toolchain for CGRA

   C++ 18 5