In-Development, be patient

The CPU implements a classic 5-stage RISC-V pipeline:

• Instruction Fetch (IF)
• Instruction Decode (ID)
• Execute (EX)
• Memory Access (MEM)
• Write Back (WB)

• 32-bit RISC-V ISA

• 5-stage pipeline

• Memory interface with byte-wise write enables

• Interrupt support with 32 interrupt lines

• Debug and trace interface

• RV32E: Designed for low-power draw and size efficiency in embedded systems.

• I: Integer addition and subtraction.

• M: Multiplication and division.

• F: Floating-point number handling.

• D: Double-precision number handling.

• C: Compressed instructions for reducing code size.

The verification environment is built using UVM 1.2 and includes:

• Memory test sequence with specific test patterns
• Interrupt test sequence
• Comprehensive scoreboarding
• Coverage collection
• Memory model with byte-enable support

The memory test verifies the following patterns:

• Alternating 1s and 0s (0x55555555)
• Alternating 0s and 1s (0xAAAAAAAA)
• All zeros (0x00000000)
• All ones (0xFFFFFFFF)
• Walking pattern (0x12345678)

• Xilinx Vivado (for synthesis)
• UVM 1.2
• GTKWave (for waveform viewing)

# Compile and run all tests make all # Run specific test make compile elaborate make simulate TEST_NAMES=cpu_memory_test # View waveforms make view # Run synthesis make synthesize

. ├── rtl/ # RTL source files │ ├── decode.sv # Decode stage │ ├── execute.sv # Execute stage │ ├── fetch.sv # Fetch stage │ ├── memory.sv # Memory stage │ └── write_back.sv # Write-back stage ├── tb/ # UVM testbench │ ├── env/ # UVM environment components │ ├── include/ # Common includes and packages │ ├── interface/ # Interface definitions │ ├── seq_lib/ # Sequence library │ └── tests/ # Test cases └── synth/ # Synthesis outputs 

Memory Test:

• Total Patterns: 5
• Test Coverage: 100%
• All patterns successfully written and read back

Target FPGA: Artix-7 (xc7a35tcsg324-1)

• LUTs: TBD
• FFs: TBD
• BRAMs: TBD
• DSPs: TBD

• Maximum Frequency: TBD MHz
• Critical Path: TBD ns

• Total Power: TBD W
• Dynamic Power: TBD W
• Static Power: TBD W