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VLSI-Shubh/README.md

Shubham Kapil Upadhyay

Digital IC Design Engineer (RTL & FPGA/ASIC Design)
MS in Electrical Engineering, Purdue University

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Philosophy

Designing practical and reliable digital systems through clear architecture, disciplined RTL development, and structured verification.

About Me

I work in digital hardware design with a focus on RTL development, pipelined processors, memory subsystems, and FPGA implementation. My work emphasizes synthesizable architecture, correctness, and timing-aware design.

What I Work On

  • RTL design in Verilog, SystemVerilog, and VHDL
  • Datapath and control architecture for processor pipelines
  • FIFO and memory system design
  • FPGA prototyping and hardware bring-up
  • Functional verification and simulation flows
  • Synthesis using open-source and industry-standard tools

Technical Toolbox

Category Tools & Skills
HDLs Verilog, SystemVerilog, VHDL
Programming Python, C/C++, Tcl, MATLAB
EDA & Simulation Vivado, Quartus, Yosys, Icarus Verilog, Verilator, GTKWave, ModelSim, Questa
Synthesis & STA Synopsys Design Compiler, Cadence Genus, OpenSTA, Timing closure
Verification UVM, SystemVerilog assertions, Cocotb, PYUVM
Analog Design Cadence Virtuoso, KLayout, MagicVLSI

Selected Projects

Round-Robin Arbiter

github.com/VLSI-Shubh/Round-Robin-Arbiter
A fair arbitration unit supporting cyclic priority rotation under concurrent requests. Includes clean control logic and simulation validation.

RISC-V RV32I Processor

github.com/VLSI-Shubh/RISCV-32I-Processor
A 32-bit RISC-V implementation featuring both single-cycle and 5-stage pipelined architectures with hazard detection, forwarding, branch logic, and verification benches.

Asynchronous FIFO

github.com/VLSI-Shubh/Asynchronous-FIFO
CDC-safe FIFO using Gray-coded pointers and multi-flop synchronization. Verified across boundary and corner cases.

Synchronous FIFO

github.com/VLSI-Shubh/Synchronous-FIFO
Single-clock FIFO with parameterized width/depth and a modular verification framework.

Sorting Algorithm Visualizer (Python)

github.com/VLSI-Shubh/Sorting-Algorithm-Visualizer-in-Python
Interactive visualization tool demonstrating sorting behavior and algorithmic flow.

Linear Feedback Shift Register (LFSR)

github.com/VLSI-Shubh/Linear-Feedback-Shift-Register-LFSR-
Pseudo-random sequence generator implemented in Verilog for test patterns and simple BIST concepts.

Smart Traffic Controller (FSM)

github.com/VLSI-Shubh/Smart-Traffic-Controller-FSM
Finite state machine with timing logic and well-structured state transitions to demonstrate control-path design.

Education

MS in Electrical Engineering
Purdue University Indianapolis
Focus Areas: VLSI design, digital systems, FPGA implementation

Experience

Firmware Engineer (Volunteer)
WinWin Labs • Remote, US
Aug 2025 – Present

Graduate Teaching Assistant (EPICS)
Purdue University • Indianapolis, IN
Aug 2024 – May 2025

Engineering Intern
Thyssenkrupp Crankshaft Company • Illinois, US
May 2024 – Aug 2024

Junior Electrical Manager
21 Knots Engineering • Mumbai, India
Feb 2022 – Jul 2023

Senior Electrical Design Engineer
Petrocil Engineering • Mumbai, India
Jun 2019 – Jan 2022

Professional Interests

  • Processor architecture and digital system design
  • Memory subsystems and timing optimization
  • Testbench development and verification methodology
  • FPGA prototyping and debugging
  • Scalable, synthesizable RTL design

Pinned Loading

  1. RISCV-32I-Processor RISCV-32I-Processor Public

    RISC-V RV32I processor implemented in Verilog, featuring both a Single-Cycle core and a fully modular 5-stage Pipelined core with hazard detection, forwarding, and synthesis support using Yosys.

    Verilog

  2. Round-Robin-Arbiter Round-Robin-Arbiter Public

    A round-robin arbiter implemented in Verilog. The design resolves simultaneous requests using a rotating priority scheme to ensure fair access among all requesters.

    Verilog

  3. GCD-Calculator GCD-Calculator Public

    Greatest Common Divisor calculator showcasing CPU-like controller + datapath architecture using subtraction-based Euclidean algorithm. Demonstrates synthesizable FSM design vs behavioral modeling t…

    Verilog

  4. Morphological-Image-Filtering-on-PYNQ-FPGA Morphological-Image-Filtering-on-PYNQ-FPGA Public

    Morphological image filtering system on PYNQ-Z2 FPGA implementing min, max, and median filters. Demonstrates HW/SW co-design with VHDL acceleration and Python orchestration for real-time image enha…

    VHDL 2

  5. Asynchronous-FIFO Asynchronous-FIFO Public

    Production-ready asynchronous FIFO buffer with independent read/write clock domains for safe CDC operations. Features Gray code pointers, dual flip-flop synchronizers, metastability prevention, and…

    Verilog

  6. Sorting-Algorithm-Visualizer-in-Python Sorting-Algorithm-Visualizer-in-Python Public

    A Python-based sorting algorithm visualizer that demonstrates Bubble, Quick, Merge, and Radix Sort with step-by-step animations using Matplotlib. Includes performance comparison, command-line custo…

    Python