🎓 Electrical Engineering Student | Research Assistant at System on Chip Lab
💡 Passionate about RTL Design, Design for Testability, and FPGA Development
I'm an enthusiastic digital hardware designer specializing in embedded systems and digital logic. Currently, I work as a Research Assistant at the System on Chip Lab, where I contribute to projects advancing Design for testability and post-silicon validation.
My core interests lie in:
- RTL Design and HDL Coding (Verilog/SystemVerilog)
- Design Verification (System Verilog, UVM ,RISCV-DV)
- Design-for-Testability (DFT), ATPG, and Scan Architectures
- FPGA Prototyping and SoC Design
I love diving deep into complex design problems—from writing synthesizable RTL to building Testability metric analyzers and testbench generators. Outside of the lab, I share my learnings through high-quality, beginner-friendly technical articles.
I regularly publish detailed technical content on digital design, testability, and VLSI systems:
