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I'm using the hardware PWM that is described on page 138 of the BCM2835-ARM-Peripherals document.

The description of the DMAC-register (page 145) indicates that one can set the FIFO-threshold at which the DREQ or PANIC-signal is sent to the Direct Memory Access hardware.

Bits 7:0 specify the DMA Threshold for the DREQ signal and bits 15:8 the DMA Threshold for the PANIC signal, so there are 8 bits for each threshold. The default value is 0x7, but there is no description on what this value actually means:

0x7 could indicate 7 free spaces or 7 filled spaces. The FIFO has a size of 8 32bit words, so it also could be the bitmask 0b0000 0111 and indicate either 3 free spaces or 3 filled spaces.

How to use this register so the signals are sent at the proper fifo thresholds?

For reference:

  1. This bcm2835-analog-audio driver kernel patch uses

    writel(0x80000E0E, chip->base + PWM_REG_DMAC);

    so it sets both thresholds to 0x0E.

  2. This Raspberry-Pi-DMA-Example sets both thresholds to 0x01 (PWM_FIFO_SIZE) with the comment:

    DREQ is activated at queue < PWM_FIFO_SIZE

  3. This "PiFM"-Implementation uses 0xF for both thresholds with the comment:

    I think this means it requests as soon as there is one free slot in the FIFO which is what we want as burst DMA would mess up our timing..

  4. This other "Raspberry PI FM Transmitter" just keeps the default 0x07 for both thresholds.

Has someone real knowledge about this or an idea for an experiment one could do to find out what it actually means?

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2 Answers 2

Reset to default
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The other answer states

1 is indeed the value for "Fill into Fifo as soon as there is a little bit of space"

but this was not very clear to me either, so I did my own experiments to find out the definition of the DMA Threshold (is it FIFO spaces or filled spots?).

I used a PWM based "DMA pacing" setup where the PWM is set to a certain frequency to generate the DREQ signals. The DMA chain is configured so that after each DREQ bound DMA transfer another unbound DMA transfer I done which reads from the system timer, so we can know when the DREQ bound DMA requests happen.

I observed that with a DMA Threshold of "N" resulted in "N+1" immediate DMA transfers before the regular DMA waiting starts. The +1 is apparently because the first written word in the FIFO is immediately consumed by the PWM hardware. Also the smallest meaningful value is "DMA-Threshold == 1". With "DMA-Threshold == 0" no DMA transfer happens at all.

Concluding, we have the following relationship

DREQ = fifo-size < DMA-Threshold

which confirms the option 2) in the question. We have DREQ is the signal routed to the DMA controller. fifo-size is the current count of words in the FIFO. DMA-Threshold are the bits 0:7 in the DMAC register of the PWM controller.

Whenever DREQ == 1, the DMA controller will do a transfer and when DREQ == 0 the DMA controller will wait.

I am pretty sure that the definition for the PANIC bits is the same, but this is difficult to test.

Note: While definition of DREQ for the PWM controller is missing in the official documentation, the documentation for DREQ of PCM and SPI controller is available (in the BCM2711 datasheet). But for SPI controller the definition is with "<=" (this is different), and for PCM it is like for PWM with "<". So the DREQ definition is incoherent among peripherals (unless the documentation is wrong).

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    Your way to measure this seems a lot better from what I remember doing back then and the answer seems logical. So to always keep the fifo filled the value should be large and generally the value for PANIC should be lower than the value for DREQ? Commented Sep 15 at 6:25
  • Yes, correct. I would say so, too. Having PANIC > DREQ will effectively disable the PANIC function. Even though I am not sure what DREQ == PANIC does mean. Is the bus priority only increase for the one transfer or all in the triggered DMA transfer? Probably it makes most sense to have PANIC < DREQ so that if the bus is so busy that if DREQ condition was missed, the PANIC is then triggered which increases priority. Commented Sep 15 at 7:13
  • One funny thing I found in the meantime is that for SPI the BCM2711 documentation states. DMA Write Request Threshold: Generate a DREQ signal to the TX DMA engine whenever the TX FIFO level is less than or equal to this amount. . So this is different. It is "<=" instead of "<". At the same time the docs state for the TX_REQ of the PCM controller (not PWM!) it is "<". So either documentation is incorrect or the DREQ definition is incoherent among peripheral devices. Commented Sep 15 at 7:28
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    Also weird, that it is 8 bits for the threshold then, because the fifo only has 8 words, so only values 0-7 are useful, because a threshold >8 would request data even though the fifo cannot take it? Commented Sep 15 at 9:22
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I did setup a DMA-Chain with a PWM (running at 19.2Mhz/1920=10000Hz in serial mode) and tried different values for the thresholds and monitored the TXFR_LEN.

Result:

  • A threshold of 1 to 10 resulted in a lot of small writes into the Fifo
  • A threshold of 11 to 15 resulted in big writes.

So i assume that 1 is indeed the value for "Fill into Fifo as soon as there is a little bit of space" and 15 will wait until the Fifo is almost empty.

I couldn't determine any "in-between" values, though, but i now know, that i want to set the threshold for the PANIC-signal higher than the threshold for the normal DREQ-signal.

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  • Please accept your own answer with a click on the tick on its left side. Only this will finish the question and it will not pop up again year for year. Commented Feb 12, 2020 at 10:25

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