Makefile issue - No rule to make target 'gcc'

Question

I have just started learning make and I am having some trouble. I want to create an executable called sortfile. Here are the relevant files: sortfile.c fileio.c fileio.h

Both sortfile.c and fileio.c use fileio.h.

Here is my makefile:

 1 CC = gcc 2 CFLAGS = -g -Wall 3 4 default: sortfile 5 6 sortfile: sortfile.o fileio.o $(CC) $(CFLAGS) -o sortfile sortfile.o fileio.o 7 8 sortfile.o: sortfile.c fileio.h $(CC) $(CFLAGS) -c sortfile.c 9 10 fileio.o: fileio.c fileio.h $(CC) $(CFLAGS) -c fileio.c 11 12 clean: 13 $(RM) sortfile *.o*~

I am getting the following error:

make: *** No rule to make target `gcc', needed by `sortfile.o'. Stop.

Brian Cain · Accepted Answer · 2014-10-23 03:13:09Z

Makefiles are of the format:

target: dependency1 dependency2 rule (command to build)

You listed the command as the set of dependencies, so make wants to try to build gcc before it can expect sortfile.o to be satisfied.

Instead of:

sortfile.o: sortfile.c fileio.h $(CC) $(CFLAGS) -c sortfile.c

you need:

sortfile.o: sortfile.c fileio.h $(CC) $(CFLAGS) -c sortfile.c

Note that normally all you really want here is something much simpler:

CFLAGS+=-g -Wall all: sortfile sortfile: sortfile.o fileio.o

This brief Makefile will work as expected with GNU Make because of implicit rules (see also).

Inserting a semicolon between the end of the prerequisite list and before the command will also work (i.e. sortfile: sortfile.o fileio.o ; $(CC) $(CFLAGS) -o sortfile sortfile.o fileio.o).
If we run out of carriage returns, that could be really handy! ;)

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