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I am working with an Intel SoC with a Hard Processor System (HPS), an Arm 64 core, and an FPGA fabric with a Nios soft processor. I would like to implement message passing between these two processors using RPMsg. Intel has a hardware mailbox IP which we have connected appropriately, and dual-port on-chip RAM has been instantiated in the hardware design and connected to the both the HPS and Nios. My understanding is that I need to develop a remoteproc driver which incorporates the mailbox notification setup, and more importantly, creates the resource table and instantiates the appropriate Virtio structures to enable the IPC. Overall, I would like:

  • Statically allocate the necessary virtio resources (vrings, message buffers) in the shared OCRAM.
  • Incorporate the platform specific mailbox driver (drivers/mailbox/mailbox-altera.c).
  • Create an interface for RPMsg (probably a char device, expose a device file to userspace for reading and writing).

I have been digging in the kernel source, and I can't figure out what parts of this framework are platform agnostic and available for my use, and which components are board specific. My questions are:

  1. Since I don't actually need to perform any life cycle management of the remote processor (Nios), I just need remoteproc to handle the virtio resources. Which rproc_ops do I need to implement?
  2. How would I go about allocating my virtio resources statically in specific physical memory regions within my remoteproc driver? Do I need to make carveouts in the resource table, or is there another way to just force the virtio resources to be in the OCRAM? How is this communicated between the processors?
  3. Assuming I have my remoteproc set up sufficiently, can I use /drivers/rpmsg/rpmsg_char.c off the shelf? Or do I need to create a different RPMsg client?
  4. In general, what kernel source files in this whole framework are platform agnostic (and available for me to use)? I can't tell

The Nios will be running a RTOS with OpenAMP or rpmsg-lite, but I'll cross that bridge after I deal with the kernel side.

Any guidance would be greatly appreciated!

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  • Scour the SoC vender's BSP documentation. I'm in a similar boat, but with Variscite iMX8mp SoM, providing Cortex A53 and Cortex M7, "connected" by rmproc. Looking to offload as much as possible to the M7, I'm analyzing feasibility of putting our web server and app Biz logic on WASM/WAMR on the M7. Biggest problem I saw was ethernet, which is completely "owned" by the A53, but then I just found this which looks promising : github.com/jtavares/rpmsg-net Commented Dec 18, 2024 at 21:26

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