UART frequency in microcontrollers [closed]

1) Why the frequency should be 16 times the baud rate?

As Chris has already pointed out in the comments, there is no clock signal, RS-232 UARTs are asynchronous systems. This means we have no idea when incoming data will start and it's a fairly safe bet that the transmitter clock will be running at a slightly different rate to the receivers. In order to cope with his the UART oversamples the incoming data so that it can come up with a reasonable measure of where the transitions in the data are. In order to oversample you need a clock running significantly faster than the data rate.

2) Can you give me an example of any Microcontroller where we set the UART frequency?

Virtually all of them will contain various registers to set this. e.g. on the LPC1768 there is the Fractional Divider Register to set the clock pre-scaler to the UART logic. Generally setting the clock frequency for the UART logic is also setting the baud rate for the output and so it may not be obvious that you're setting a clock to 16 times the baud rate.

3) What the purpose of setting clock frequency to UART if we have timers? Like we generate baud rate in simple 89c52 through Timer 1 and we don't set any frequency.

So that you can run each UART at a different baud rate without using up all of your timers?

4) What's the idea of setting the baud rate with timer like we do in 89c5x. How it is linked to UART frequency?

No idea, not used the part but that seems a little odd.

5) RS-232 is recommended standard 232 and UART is physical. Hardware does parallel-serial and serial-parallel conversions. Am I right?

Yes, the UART has an 8 bit transmit and receive buffer, the processor only deals with bytes of data, the UART hardware handles converting to serial and back.

6) Does UART contain a counter, so that after the start bit it waits for 8 cycles and then after each 16 cycles, the samples are taken from RX line to detect the bit?

It contains a state machine that tracks the current point in the transmit/receive cycle. This state machine will contain both counters and logic to detect transitions, start and stop bits and generate/check parity bits. Unless you want to design your own UART you don't need to worry about what exactly is going on inside that state machine. If you do want to design your own UART then that's a whole new subject.

The question and some of the answers are confusing "clock", "frequency", and "baud rate".

As explained, there is a clock inside the UART that is usually 16 times the desired baud rate. Back when I had hair, this clock was provided to the UART by a hardware divider, usually set by DIP switches, from a crystal oscillator.

But a UART like a 16550 or the UART in a microcontroller contains the divider circuit. When you "set the baud rate" by writing to a UART register, you are setting the divisor. The input is a high frequency clock, often the processor clock.

So a 16550 will often have an input from a 1.8432 MHz crystal oscillator. Divide that by 16, and you get 115200 baud, the fastest speed available with that UART using that input. To get that baud rate, you would set the UART's baud rate divisor to 1. Set the divisor to 2, and you get 57600 baud. Set it to three and you get 38400 baud, etc.

Fancier UARTS have "fractional divisor" logic, which allow you to get standard baud rates (or close to them) from an input oscillator that isn't an integer multiple of the baud rate.

Some of the design principles of UARTs go back to the days when the combined cost of a crystal, a divide-by three circuit, and a power-of-two frequency divider would be lower than the cost of a fully-programmable frequency divider.

The most versatile way to design a UART would be to use separate programmable frequency dividers for transmit and receive, each set for 1x the baud rate, and "jam" each at a programmable count when the corresponding side of the UART is idle. Doing things that way, however, would require the use of two separate fully-programmable frequency dividers. It's cheaper to have one programmable divider shared between transmit and receive, but have it run fast enough that both the transmitter and receiver can independently divide it down further.