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I have a Verilog program to implement an 8-bit PISO register:

module PISO(input clk ,input [7:0] par_in, output reg out_bit); reg [7:0] mem = 8'b00000000; reg [2:0] count = 3'b000; always @ (posedge clk) begin if (count == 3'b000) begin mem <= par_in; count <= 3'b111; end else begin out_bit <= mem[0]; mem <= mem >> 1; count <= count - 1; end end endmodule

the problem is all outputs through the output register out_bit work fine, but the MSB, read at the very end after 7 right shifts (7 clock cycles) is read as 0, no matter the value.

For example, if the input given is 10101010, the outputs are:

Bit_out:0 Bit_out:1 Bit_out:0 Bit_out:1 Bit_out:0 Bit_out:1 Bit_out:0 Bit_out:0 //Incorrectly read MSB

I have tried all manner of fixes such as changing all non blocking assignments to blocking assignments, and ensured all registers are correctly initialised, but the problem persists.

I am using iverilog version 11. How do i fix the problem with the MSB? Is it dependent on the Verilog compiler being used?

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1 Answer 1

Reset to default
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module PISO(input clk ,input [7:0] par_in, output reg out_bit); ... always @ (posedge clk) begin if (count == 3'b000) begin mem <= par_in; count <= 3'b111; end else begin ... end end endmodule

You never assign any value to out_bit when the count is 0. So on that count, out_bit just stays the same as it was in the previous cycle.

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  • \$\begingroup\$ i see....will increasing the count bit to 4 bits and counting upto 1000 before resetting to 0 solve the issue? \$\endgroup\$ Commented Nov 23, 2024 at 18:33
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    \$\begingroup\$ @Rotas Just move the out_bit assignment out of the if-else statement \$\endgroup\$ Commented Nov 23, 2024 at 18:34
  • \$\begingroup\$ @Rotas, in that case you will only get 8 bits of output every 9 cycles --- and one of the bits will just stick for two cycles. Why not just assign something appropriate to out_bit when count is 0? \$\endgroup\$ Commented Nov 23, 2024 at 18:34
  • \$\begingroup\$ @Tom Carpenter ah ok....ill try that, thank you for your help! \$\endgroup\$ Commented Nov 23, 2024 at 18:35
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    \$\begingroup\$ Yes. Assuming you're doing this in an FPGA that's exactly why they use 0-hold-time registers. \$\endgroup\$ Commented Nov 23, 2024 at 18:41

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