Timeline for How to constrain a clock signal out from a multiplexer
Current License: CC BY-SA 4.0
8 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 14, 2021 at 18:26 | answer | added | Anurag Atmakuri | timeline score: 0 | |
| Jul 26, 2018 at 17:18 | comment | added | camillo_benso | Ali that's not a gated clock design, I am not involving any enable nor inhibiting the clock | |
| Jul 26, 2018 at 17:10 | comment | added | Ale..chenski | This is a bad "gated clock" design, and it can't be constrained. See Dave's answer. | |
| Jul 26, 2018 at 16:45 | comment | added | camillo_benso | clk_out clocks a module which has a set of inputs also dependent to the select pin of the mux. I mean that inputs are driven coherently with the selection of the mux | |
| Jul 26, 2018 at 16:43 | answer | added | Dave Tweed | timeline score: 3 | |
| Jul 26, 2018 at 16:42 | comment | added | The Photon | You should check if the clock management blocks/tiles/whatever in your FPGA offer a glitch-free clock multiplexer. | |
| Jul 26, 2018 at 16:24 | comment | added | Elliot Alderson | What do you mean by "if it talks...with the logic driven by clk_in and ext_clk"? How are you planning to use clk_out? This sounds very dangerous to me. | |
| Jul 26, 2018 at 16:01 | history | asked | camillo_benso | CC BY-SA 4.0 |