How to constrain a clock signal out from a multiplexer

Question

How would you constrain this design?

ext_clk and clk_in are asynchronous to each other. clk_div is derived by clk_in with double period.

clk_out may be driven by either clk_in and ext_clk, according to the selector pin of the multiplexer.

This is what I would do:

create_clock -period 42 -waveform {0 21} [get_ports "clk_in"] create_clock -period 300 -waveform {0 21} [get_ports "ext_clk"] create_generated_clock -name clk_out -source [get_ports "clk_in"] -divide_by 2 [get_pins "xmux/y"] create_generated_clock -name clk_out -source [get_ports "ext_clk"] [get_pins "xmux/y"] -add

I am not totally sure this is the proper way to constrain this design. What do you think will be the impact of these constraints to the CTS generation in terms of balancing for the logic clocked by clk_out if it talks, mutually exclusive, with the logic driven by clk_in and ext_clk?

What do you mean by "if it talks...with the logic driven by clk_in and ext_clk"? How are you planning to use clk_out? This sounds very dangerous to me. — Elliot Alderson
– Elliot Alderson, Commented Jul 26, 2018 at 16:24
You should check if the clock management blocks/tiles/whatever in your FPGA offer a glitch-free clock multiplexer. — The Photon
– The Photon, Commented Jul 26, 2018 at 16:42
clk_out clocks a module which has a set of inputs also dependent to the select pin of the mux. I mean that inputs are driven coherently with the selection of the mux — camillo_benso
– camillo_benso, Commented Jul 26, 2018 at 16:45
This is a bad "gated clock" design, and it can't be constrained. See Dave's answer. — Ale..chenski
– Ale..chenski, Commented Jul 26, 2018 at 17:10
Ali that's not a gated clock design, I am not involving any enable nor inhibiting the clock — camillo_benso
– camillo_benso, Commented Jul 26, 2018 at 17:18

Dave Tweed · Accepted Answer · 2018-07-26 16:43:45Z

If the clocks are asynchronous (to each other), there are no meaningful constraints you can place between them.

You need to create a constraint for clk_out that represents the "worst case" for any of the possible clock inputs, and use that to evaluate the rest of the design.

The rest of the design must also be able to handle the timing violations that will occur when you change the control on the mux.

Note that there are more sophisticated (synchronous) clock switching techniques that can avoid creating "runt pulses", etc. that will make the design of the downstream logic simpler. These are usually built into the FPGA/ASIC vendor's clock management IP. You might want to read up on that.

Thanks Dave, with "worst case" you mean shaping clk_out with the highest frequency that can come from clk_in or ext_clk i guess. The switching technique is not part of the problem at the moment, actually I have already implemented it safely, in order to avoid any case of glitch (that mux is just for representation purposes, it's not really there) — camillo_benso
– camillo_benso, Commented Jul 26, 2018 at 17:22
I can only comment on what I can see. The quality of the question pretty much dictates the quality of the answers. — Dave Tweed
– Dave Tweed, Commented Jul 26, 2018 at 18:46

Tom Carpenter · Accepted Answer · 2021-01-14 22:34:23Z

Clock definitions seem fine, although generated clocks should have different names to identify which one is ext_clk based and vice versa.

In your case, clk_out is where you define the generated clocks based on ext_clk and clk_div2. This ensures both clocks are active at the output. However, since you mentioned these are asynchronous, you need to set that relationship between them. Regardless of that, Mux only selects one clock at a given time, so there can't be clocks between these 2. So that leads us to logically exclusive relationship between the two generated clocks. For all clocks, talking outside of this mux, you need asynchronous exception.

set_clock_groups -asynchronous -group1 {ext_clk} -group2 {clk_div2}

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