Timeline for How do I build and simulate a T Flip-Flop without a reset in SystemVerilog?
Current License: CC BY-SA 4.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 1, 2021 at 5:37 | vote | accept | Shashank V M | ||
| Mar 1, 2021 at 5:37 | comment | added | Shashank V M | Thanks for this great answer! I am still a student and have not got a chance to work in the VLSI Design industry yet. So it is new information to me that a T Flip-Flop without reset is useless, although I had suspected it would be useless in my answer here: electronics.stackexchange.com/a/540545/238188 | |
| Mar 1, 2021 at 2:32 | comment | added | Elliot Alderson | I think you will find that there are many questions on this site that are only of academic interest. Sometimes barely even that. Often we get obscure homework questions that must be solved in some specific manner. | |
| Mar 1, 2021 at 1:40 | history | answered | Matt | CC BY-SA 4.0 |