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Electrical Engineering
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Matt
  • Member for 7 years, 7 months
  • Last seen more than 2 years ago
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5
Why would an AND gate need six transistors?
Nov 22, 2020
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4
Why not implement 1Gbps, when all I need is 20Mbps?
May 20, 2018
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4
FSM sequence detector in Verilog
Apr 10, 2019
answer
4
Do more logic gates in series mean more slowing of the output result?
Jul 27, 2021
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3
Problem with PIPO Register - Verilog
Apr 16, 2021
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2
Why can't I use assign operator on multiple bits?
May 14, 2018
answer
2
mips single-cycle branch verilog
Sep 2, 2018
answer
2
Verilog circuit not synchronous
Oct 13, 2018
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2
Circuit to "zoom in" on mV fluctuations of a DC signal?
Apr 17, 2019
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2
Through node analysis, how do i find the unknown?
Mar 23, 2021

Top network posts

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How to avoid stopping when I play a wrong note on the piano