Timeline for How does Asynchronous DRAM perform self-timing

8 events

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Sep 30, 2021 at 5:56	comment	added	Mitu Raj		There is no handshaking between DRAM Controller and DRAM. DRAM has strict timing requirements. It's the job of DRAM Controller to make sure that this timings are met. User/Host talks with DRAM controller. DRAM controller will tell the user, whether the pending write/read operations on DRAM are completed, whether any further transaction can be accepted etc. There is handshake in the domain between User and DRAM Controller.
Sep 30, 2021 at 5:53	history	became hot network question
Sep 29, 2021 at 21:38	vote	accept	Oliver Young
Sep 29, 2021 at 21:00	answer	added	Dave Tweed		timeline score: 5
Sep 29, 2021 at 20:25	comment	added	Bimpelrekkie		And nearly every RAM module contains a small read-only memory with the required timing information. This information is read and used to program the memory controller to use the correct timings.
Sep 29, 2021 at 20:23	comment	added	Justme		But DRAMs don't know that and do not report back with an acknowledge and do not do self timing. The controller must output control signals such as RAS and CAS that are suitably slow for the used DRAM, as if the timing is too fast then it may not work. SDRAMs and thus SDRAM controller is synchronous to the clock so as long as the signals are certain amount of clocks long what the SDRAM needs then it will work.
S Sep 29, 2021 at 20:14	review	First questions
Sep 29, 2021 at 22:38
S Sep 29, 2021 at 20:14	history	asked	Oliver Young	CC BY-SA 4.0