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The original question was deemed lack of focus. This post is specifically about dram chip.

When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and acknowledge back to DRAM controller? Writing a DRAM cell (one transistor + one capacitor) takes a certain amount of time to finish, how does DRAM itself performs self-timing and inform DRAM control that the write is complete? (I guess this question also applies to SDRAM? Even if SDRAM has an synchronous interface, at its core it still needs to do self-timing.)

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    \$\begingroup\$ But DRAMs don't know that and do not report back with an acknowledge and do not do self timing. The controller must output control signals such as RAS and CAS that are suitably slow for the used DRAM, as if the timing is too fast then it may not work. SDRAMs and thus SDRAM controller is synchronous to the clock so as long as the signals are certain amount of clocks long what the SDRAM needs then it will work. \$\endgroup\$ Commented Sep 29, 2021 at 20:23
  • \$\begingroup\$ And nearly every RAM module contains a small read-only memory with the required timing information. This information is read and used to program the memory controller to use the correct timings. \$\endgroup\$ Commented Sep 29, 2021 at 20:25
  • \$\begingroup\$ There is no handshaking between DRAM Controller and DRAM. DRAM has strict timing requirements. It's the job of DRAM Controller to make sure that this timings are met. User/Host talks with DRAM controller. DRAM controller will tell the user, whether the pending write/read operations on DRAM are completed, whether any further transaction can be accepted etc. There is handshake in the domain between User and DRAM Controller. \$\endgroup\$ Commented Sep 30, 2021 at 5:56

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Asynchronous DRAM is not self-timed at all. The DRAM controller must meet all of the timing requirements specified in the DRAM datasheet, or the operation will simply fail in some way.

Even with modern synchronous DRAM chips, there is no "handshake" between the memory controller and the DRAM chips. The controller must generate all of the control signals with the required timing relationships. Sometimes, especially with the memory modules used in PCs, there is a small ROM that contains the timing requirements for the chips on that module.

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  • \$\begingroup\$ Thank you @Dave Tweed for the explanation, very helpful. Assuming the timing requirement for a write is 1.5 ns and cpu clock period is 1 ns, so the dram controller must hold all control signals for 2 clock cycle and on the third clock cycle, dram controller could assume the data is valid on the data bus and latch it into its own register? \$\endgroup\$ Commented Sep 29, 2021 at 21:17
  • \$\begingroup\$ The question makes no sense. We were talking about the protocol between the memory controller and the actual memory chips. You now appear to be asking about communication between a CPU and the memory controller, which is a completely independent topic. \$\endgroup\$ Commented Sep 30, 2021 at 1:17
  • \$\begingroup\$ I was assuming dram controller is built on the same chip as cpu and dram controller runs at same clock rate as cpu. \$\endgroup\$ Commented Sep 30, 2021 at 2:11
  • \$\begingroup\$ Well, yes, in modern desktop CPUs, the memory controller (for SDRAM) is generally part of the CPU chip, but they almost aways operate at different clock rates. Like I said before, if you want to understand the protocol, you need to look at an SDRAM datasheet. It is not simple. \$\endgroup\$ Commented Sep 30, 2021 at 3:19
  • \$\begingroup\$ I see. Thank you for the recommendation! \$\endgroup\$ Commented Sep 30, 2021 at 3:44

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