Timeline for Use SDC format for timing constraints on Xilinx CPLDs
Current License: CC BY-SA 4.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Oct 11, 2021 at 20:20 | vote | accept | Ben Voigt | ||
| Oct 11, 2021 at 20:18 | comment | added | Ben Voigt | @MituRaj: Except Vivado only works on a handful of product families, not including any CPLDs. ISE is still the last/only development tool listed on the CPLD product pages. | |
| Oct 11, 2021 at 18:27 | comment | added | Mitu Raj | Hmm no... that's one reason why Xilinx dumped ISE big time. | |
| Oct 11, 2021 at 17:45 | answer | added | Dave Tweed | timeline score: 1 | |
| Oct 11, 2021 at 17:36 | comment | added | Ben Voigt | I think your comments are now a complete answer: There is no way to pass SDC constraints to the synthesis tools included in Xilinx ISE Design Suite, but Xilinx ISE is capable of integrating with one or more separately-installed-and-licensed tools that do use SDC. | |
| Oct 11, 2021 at 17:35 | comment | added | Ben Voigt | @DaveTweed: Thanks! Sorry for asking what seems to be such a basic question but after seeing (and using) Modelsim Altera Edition (Lite), Modelsim Altera Edition, Modelsim Modelsim Intel Edition, Modelsim Intel Edition (Lite), Xilinx Edition (Lite), Mentor Modelsim (Lite) etc I can no longer assume that a product described in the vendor documentation is referring to the popular separately-sold third-party product having that name. | |
| Oct 11, 2021 at 17:27 | comment | added | Dave Tweed | Synplify is a Synopsys product. I think it was basically the only 3rd-party synthesis tool that Xilinx officially supported at the time, which is why the information about .sdc files appears in the Xilinx User Guides related to timing analysis. I can find nothing in the User Guides that indicates that .sdc files can be used with anything other than Synplify. | |
| Oct 11, 2021 at 17:21 | comment | added | Ben Voigt | What confuses me is that there are multiple third-party tools that support Xilinx parts (Aldec, Synopsys, Mentor, etc) but use of Synplify is detailed in Xilinx's own documentation. | |
| Oct 11, 2021 at 16:40 | comment | added | Ben Voigt | @DaveTweed I saw some information to that extent but I haven't been able to exactly figure out the relationship between Xilinx ISE and Synplify. I'm using ISE in the sense of "ISE Design Suite" not a single tool in that suite. Are XST and Synplify two different synthesis tools within the Xilinx Design Suite eco-system, or is Synplify a paid third-party tool with support for Xilinx devices and integration with the ISE-provided programmer etc? | |
| Oct 11, 2021 at 15:54 | comment | added | Dave Tweed | AFAIK, you can only use .sdc files with Synplify synthesis, not with ISE synthesis. If you're using ISE synthesis, then you'll have to find or create a way to translate .sdc to .ucf or .xcf I've never seen such a tool -- most are oriented toward forward migration, in the other direction. | |
| Oct 11, 2021 at 15:36 | history | asked | Ben Voigt | CC BY-SA 4.0 |