Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers.
I have existing hardware description source code (VHDL) and I/O timing specifications (SDC). The CoolRunner-II CPLD family isn't supported by Vivado so I'm using ISE.
Adding VHDL files to a design is easy. I don't have any pin assignments yet, because I'm still evaluating which CPLD parts are worth going through place-and-route with my PCB team, so I'll let the fitter auto-select pin assignments for now. But where do I tell ISE to read SDC timing constraints from a text file?
I've found numerous mentions of SDC and XDC constraints on the Xilinx site and documentation of the individual commands, but none of the documentation I've found has covered step #1 -- how to pass an SDC file to the synthesis tool.
I'm not looking for a way to input timing constraints graphically, or use an alternate constraint language such as UCF. SDC is the standard vendor-independent timing language and I already have the constraints written.
Is it possible to pass SDC constraints to the ISE synthesis tools? Do I need to upgrade from WebPack to a paid license? What steps do I go through in ISE to add an SDC file to the project and use it for timing analysis?
