Timeline for VHDL: is this RAM design over-complicated?
Current License: CC BY-SA 4.0
19 events
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| Aug 4, 2024 at 17:08 | history | edited | user224802 | CC BY-SA 4.0 | added 4780 characters in body |
| Aug 3, 2024 at 22:01 | history | edited | user224802 | CC BY-SA 4.0 | added 129 characters in body |
| Aug 3, 2024 at 21:50 | history | edited | user224802 | CC BY-SA 4.0 | added 373 characters in body |
| Aug 3, 2024 at 19:48 | history | edited | user224802 | CC BY-SA 4.0 | added 373 characters in body |
| Aug 3, 2024 at 17:20 | history | edited | user224802 | CC BY-SA 4.0 | added 5079 characters in body |
| Aug 3, 2024 at 12:10 | comment | added | the busybee | Apparently, yes. :-D At least for the way you build. -- One additional experiment is the removal of the reset function. Depending on your target, it might reduce some more. -- To learn how much complexity comes from what input, you can even go all the way down to a single 1 bit memory, and from there double width or number of stored words. You could jot down the results in a table to evaluate how it scales. -- However, if your target provides embedded RAM, probably it is best to learn how to use that. I'd expect that several application notes exist. | |
| Aug 2, 2024 at 21:23 | comment | added | user224802 | @busybee I made the simpler design and edited my question to include it. The architecture of the schematic is quite the same, the only difference consisting of fewer LUTs and wires used. Does it mean that this complexity is normal and unavoidable ? | |
| Aug 2, 2024 at 21:21 | history | edited | user224802 | CC BY-SA 4.0 | deleted 56 characters in body |
| Aug 2, 2024 at 21:19 | comment | added | user224802 | @ChesterGillon I also added a testbench and its simulation result, some things look suspicious | |
| Aug 2, 2024 at 21:18 | comment | added | user224802 | @ChesterGillon I made the fix, as you suspected it confused the synthesis but I don't understand why, shifting was supposed to make the RAM byte-addressable instead of word-addressable. Consider the signal "10100", shifting it by 2 is supposed to return index=5. Also I changed a bit the design so readings are refreshed after a writing, before readings were refreshed only when the addr signal was changing. | |
| Aug 2, 2024 at 21:14 | history | edited | user224802 | CC BY-SA 4.0 | added 1630 characters in body |
| Aug 2, 2024 at 20:29 | answer | added | Peter Green | timeline score: 0 | |
| Aug 2, 2024 at 20:27 | history | edited | user224802 | CC BY-SA 4.0 | added 2070 characters in body |
| Aug 2, 2024 at 20:21 | comment | added | Chester Gillon | In the updated code the memory array has indices 0..5. Yet the read and write have index := to_integer(shift_left(unsigned(addr),2));. Which as far as I tell means that only indices 0 and 4 into the ``memory` array will be used. The synthesis probably recognises that, resulting in only two 32-bit memory indices being used which explains why only 64 FFs are used. Do you have a test bench to check the updated code functions as expected? | |
| Aug 2, 2024 at 20:08 | history | edited | user224802 | CC BY-SA 4.0 | modified the VHDL design |
| Aug 2, 2024 at 12:20 | answer | added | Dave Tweed | timeline score: 0 | |
| Aug 2, 2024 at 7:16 | answer | added | Chester Gillon | timeline score: 1 | |
| Aug 2, 2024 at 5:49 | comment | added | the busybee | To get an idea on complexity, did you try to synthesize a much simpler design with only 8 bit data bus width? Some complexity might come from the necessary multiplexers because of your memory core organized as 8 bit data in contrast to the entity's 32 bit data. Please edit your question to add your results. | |
| Aug 1, 2024 at 21:58 | history | asked | user224802 | CC BY-SA 4.0 |