Read decimal value of a 4-bit binary input

Loops in HDL are a tricky thing to use in a synthesizable manner. I would recommend simply reading in the input bits as a binary number, compare with 9, if it is greater subtract 10.

Solution 1:
The Double Dabble Algorithm. Electronics.StackExchange lists many Q&A for this topic:

• Fastest way to get integer mod 10 and integer divide 10?
• Binary to BCD converison
• VHDL - Convert from binary/integer to BCD and display it on the 7-segment display
• Displaying a 2-digit integer on two 7-segment display

StackOverflow is also full of results.

Solution 2
Using a systolic array of digit converts.

Let's convert a n-bit binary input into m digits. Each systolic element has a Clock and Reset input as well as a 1-bit Shift_in signal. It generates a 4-bit BCD encoded Digit and a Shift_out signal (aka overflow).

This is the element's port declaration:

subtype T_BCD : UNSIGNED(3 downto 0); entity arith_convert_bin2bcd_element is port ( Clock : IN STD_LOGIC; Reset : IN STD_LOGIC; Shift_en : IN STD_LOGIC; Shift_in : IN STD_LOGIC; Shift_out : OUT STD_LOGIC; BCD : OUT T_BCD ); end; 

How does it work?

On every shift operation, it calculates:
\$Digit = Digit * 2 + Shift_{in}\$

\$Shift_{out} = \begin{cases} 1 &\text{when}\,\, (Digit \ge 10) \\ 0 & else\end{cases}\$

\$Digit = \begin{cases} Digit-10 &\text{when}\,\, (Digit \ge 10) \\ Digit & else\end{cases}\$

architecture rtl of arith_convert_bin2bcd_element is signal Digit_ext : UNSIGNED(T_BCD'length downto 0); signal Digit_ov : STD_LOGIC; signal Digit_d : T_BCD := "0000"; begin Digit_ext <= Digit_d & Shift_in; Digit_ov <= to_sl(Digit_ext > 9); Shift_out <= Digit_ov;-- when rising_edge(Clock); -- register overflow process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Digit_d <= "0000"; elsif (Shift_en = '1') then if (Digit_ov = '0') then Digit_d <= Digit_ext(Digit_d'range); else Digit_d <= resize(Digit_ext - 10, Digit_d'length); end if; end if; end if; end process; BCD <= Digit_d; end; 

Now you can combine as many element as needed to convert a binary number. What's needed for this task?

• a FSM with 3-4 states: idle, [complement], convert, complete
  complement is only needed if you input can be negative
• a counter that counts for n shift operations
• a parallel-in/serial-out register, that shifts or rotates left (to the highest bit)
• a generate statement, that generates m element instances

And here is the systolic array wiring and control logic:

entity arith_convert_bin2bcd is generic ( IS_SIGNED : BOOLEAN := FALSE; BITS : POSITIVE := 8; DIGITS : POSITIVE := 3 ); port ( Clock : IN STD_LOGIC; Reset : IN STD_LOGIC; Start : IN STD_LOGIC; Complete : OUT STD_LOGIC; Binary : IN STD_LOGIC_VECTOR(BITS - 1 DOWNTO 0); BCDDigits : OUT T_BCD_VECTOR(DIGITS - 1 DOWNTO 0); Sign : OUT STD_LOGIC ); end; architecture rtl of arith_convert_bin2bcd is type T_STATE is (ST_IDLE, ST_CPL, ST_CONVERT, ST_COMPLETE); signal State : T_STATE := ST_IDLE; signal NextState : T_STATE; signal Digit_Shift_en : STD_LOGIC; signal Digit_Shift_in : STD_LOGIC_VECTOR(DIGITS downto 0); signal Binary_en : STD_LOGIC; signal Binary_cpl : STD_LOGIC; signal Binary_rl : STD_LOGIC; signal Binary_d : STD_LOGIC_VECTOR(BITS - 1 downto 0) := (others => '0'); signal Binary_Sign : STD_LOGIC; signal Sign_d : STD_LOGIC := '0'; signal ShiftCounter_rst : STD_LOGIC; signal ShiftCounter_eq : STD_LOGIC; signal ShiftCounter_s : SIGNED(log2ceilnz(BITS - 1) downto 0) := (others => '0'); begin process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then State <= ST_IDLE; else State <= NextState; end if; end if; end process; process(State, Start, Binary_Sign, ShiftCounter_eq) begin NextState <= State; Complete <= '0'; Binary_en <= '0'; Binary_cpl <= '0'; Binary_rl <= '0'; Digit_Shift_en <= '0'; ShiftCounter_rst <= '1'; case State is when ST_IDLE => if (Start = '1') then Binary_en <= '1'; if (Binary_Sign = '1') then NextState <= ST_CPL; else NextState <= ST_CONVERT; end if; end if; when ST_CPL => Binary_cpl <= '1'; NextState <= ST_CONVERT; when ST_CONVERT => Binary_rl <= '1'; Digit_Shift_en <= '1'; ShiftCounter_rst <= '0'; if (ShiftCounter_eq = '1') then NextState <= ST_COMPLETE; end if; when ST_COMPLETE => Complete <= '1'; NextState <= ST_IDLE; end case; end process; process(Clock) begin if rising_edge(Clock) then if (Reset = '1') then Binary_d <= (others => '0'); elsif (Binary_en = '1') then Binary_d <= Binary; Sign_d <= '0'; elsif (Binary_cpl = '1') then Binary_d <= cpl(Binary_d); -- 2's component Sign_d <= '1'; elsif (Binary_rl = '1') then Binary_d <= Binary_d(Binary_d'high - 1 downto 0) & Binary_d(Binary_d'high); end if; end if; end process; Sign <= Sign_d; Binary_Sign <= Binary_d(Binary_d'high); Digit_Shift_in(0) <= Binary_d(Binary_d'high); -- count shift operations from BITS-2 downto -1 ShiftCounter_s <= counter_dec(ShiftCounter_s, ShiftCounter_rst, '1', BITS - 2) when rising_edge(Clock); ShiftCounter_eq <= ShiftCounter_s(ShiftCounter_s'high); -- generate DIGITS many systolic elements genDigits : for i in 0 to DIGITS - 1 generate Digit : entity PoC.arith_convert_bin2bcd_element port map ( Clock => Clock, Reset => Reset, Shift_en => Digit_Shift_en, Shift_in => Digit_Shift_in(i), Shift_out => Digit_Shift_in(i + 1), BCD => BCDDigits(i) ); end generate; end; 

And here is a simulation (clickable):