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I Have Few Doubts on AMBA Bus Architecture and its clocks

I am working on Propriety SOC with non-detailed docs , the SOC is based on ARM9 Architecture which has peripherals connected to it through AMBA2.0

Every Peripheral (lets say UART) needs a clock which is given after prescaling and postscaling through PLL and fed to the respective peripheral, so we are clear that we need a clock for a peripheral to work

As these Peripherals are connected over a APB Bus, each has a PCLK input which is connected to the core through the matrix

Now my doubt is how APB master(the arm core) is handling the PCLK while its been generated from separate block APB clock generator, is PCLK generated by slave in contrary ?? does the peripheral work with PCLK itself ???

if possible suggest me some references on AMBA in arm based SOC

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We must understand the difference between interface clock and functional clock APB clock is the interface clock Each peripheral receives two clocks: interface clock (or APB bus clock) and functional clock. Interface clock is used to read/write the registers of the peripheral. In other words, your APB bus clock is needed to read/write your UART registers for programming. On the other hand, functional clock is used to operate the peripheral. An UART sends/receives data when the functional clock is enabled. In some cases the function clock is derived from interface clock, but in most cases functional clock is derived from other clock source. (The selection of clock source is programmable in most SoCs). In order to operate a peripheral, we need both interface clock ('to program registers of the peripheral) and functional clock. During sleep, we disable the interface clock for the peripheral. Functional clock may or may not be disabled during sleep depending on use cases.

All clocks (interface and functional clocks) are generated by several PLLs inside clock generation module. ARM core does not generate any clock.

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